[PPT] - Chapter 11 h Addition Arithmetic Multiplication Building Blocks PowerPoint Presentation

SLIDE 1

1

h

Digital IC-Design

Chapter 11 Arithmetic Building Blocks g

Overview

Addition Multiplication

Digital Processor

Memory Input Output Control Data Path

REG

IN

Example: Wave Digital Filter (WDF)

NEG MULT ROM REG REG APU CTRL

SEQUENCER

Data Bus Coefficient Bus Read Address

REG ADD

CTRL Bus OUT

SLIDE 2

2 Data Path Design

Bit Bit Bit Bit Bit Bit

IN

Bit-sliced design One slice

XOR Adder Register Register Bit0 Bit1 Bit2 Bit3 Bit4 Bit5

CTRL

per bit

Register Register

OUT

Bit-Sliced Data Path

Register XOR Adder Register

Number Representation

Sign Magnitude One´s Complem. Two´s Complem.

Dec Pos Neg Dec Pos Neg Dec Pos Neg Dec. Pos. Neg. Dec. Pos. Neg. Dec. Pos. Neg.

0 0000 1000 0 0000 1111 0 0000 1 0001 1001 1 0001 1110 1 0001 1111 2 0010 1010 2 0010 1101 2 0010 1110 3 0011 1011 3 0011 1100 3 0011 1101 4 0100 1100 4 0100 1011 4 0100 1100 5 0101 1101 5 0101 1010 5 0101 1011 6 0110 1110 6 0110 1001 6 0110 1010 7 0111 1111 7 0111 1000 7 0111 1001 7 0111 1111 7 0111 1000 7 0111 1001 8 1000

Two Zeros Two Zeros One Zero One more neg.

Two´s Complem.

Two’s complement conversion

Invert the number Add 1 LSB iti

Dec. Pos. Neg.

0 0000 1 0001 1111 2 0010 1110 3 0011 1101 4 0100 1100 5 0101 1011

Add 1 on LSB position Example:

1 1 6

5 0101 1011 6 0110 1010 7 0111 1001 8 1000

1 1 6 1 1 1

6

SLIDE 3

3 Addition is the most common arithmetic ti i di it l

Addition

peration in digital processors

Also the basis of most other arithmetic

perations like

multiplication division division square root …

Binary Adder Cell (Two’s Complement)

A B C i S C o 0 Delete

A B

HA

Co

0 Delete 1 1 0 Delete 1 1 0 Propagate 1 1 1 Propagate 1 1 0 Propagate 1 1 1 Propagate

S Ci A S B

FA

Co

1 1 1 Propagate 1 1 1 Generate 1 1 1 1 1 Generate

Ci A S B Co

Binary Adder S A B = ⊕ Half Adder

A B

HA

Co

C

AB S A B C = = ⊕ ⊕ = Full adder

S Ci A S B

FA

Co

ABC

ABC ABC ABC C AB AC BC = + + + = + +

Ci A S B Co

D A B P A B = ⊕ Delete, Propagate

Generate, Propagate, and Delete

Functions

P A B G AB S A B C P C = ⊕ = = ⊕ ⊕ = ⊕ Propagate, Generate,

f A and B

1 1 1 1 1 1 1 A+ B B A

( ) ( )

C

AB AC BC AB A B C AB AB A B C G PC = + + = + + = = + + ⊕ = +

Redundant

SLIDE 4

4 Ripple Carry Adder

A0 B0 A4 A2 A1 B4 B2 B1 FA FA FA FA A3 B3 FA C Worst case delay

Critical path

( 1) t N t t +

S0 S4 S2 S1 FA FA FA FA S3 FA Ci,0 Co,0 Co,3 Co,2 Co,1 Co,4

Fast carry more important than fast sum

( 1) . . ( )

adder carry sum adder

t N t t i e t N = − + = Ο Static CMOS Full Adder

B A C A A B

VDD VDD

C B A B A A B B A C C C C A A A B B B S

VDD

S Co Co A

VDD

Static CMOS Full Adder - Mirror Adder

One stage operation (inverse)

D P

C B A B A A B B C C C C A A B B B

VDD VDD

S Co C A B

VDD

A

D P

Minimum sized transistors in sum

A

G P

The Mirror Adder

The NMOS and PMOS chains are completely symmetrical

Focus on carry stage Focus on carry stage

Max two stacked transistors in the carry generation Transistors connected to Ci are placed closest to the output Transistors in the carry stage have to be optimized for speed Transistors in the sum stage can be minimal size In layout, focus on capacitance at node Co

SLIDE 5

5 One Stage Addition

Eliminate carry inversion A B A B

De Morgan Law´ s

S Ci Co FA S Ci Co FA

( , , ) ( , , ) ( , , ) ( , , ) S A B C S A B C C A B C C A B C = =

Chapter 11 h

Digital IC-Design

Arithmetic Building Blocks Cont.

One Stage Addition

Even Odd

FA FA FA FA FA A0 B0 A4 A2 A1 B4 B2 B1 S0 S4 S2 S1 A3 B3 S3 Ci,0 Co,0 Co,3 Co,2 Co,1 Co,4

Two different cells

B A C 0 C 1 A B

VDD VDD

B A B A

Improved Carry Stage

Few transistors in

VDD VDD

A B Co,0 Co,1 B A Ci,1 B A B A

Few transistors in carry stage P and G precalculated before carry

P P G G Co,0 Co,1 P P G G Ci,1

before carry arrives

SLIDE 6

6 Carry Chain

( ) ( )

C

AB C AB C G P A C B A B + ⊕ = + = + = +

No inversion of A and B needed

P G Co,0 Co,1 P G Ci,1

VDD VDD

P G P G P G A B A B P G

Example – Generate, A= 1 and B= 1

( ) ( )

C

AB C AB C G P A C B A B + ⊕ = + = + = +

P G Co,0 Co,1 P G Ci,1

VDD VDD

1 1 1 1 1 1 1 1 1

P G P G P G A B A B P G

1 1

Example – Generate, A= 0 and B= 0

( ) ( )

C

AB C AB C G P A C B A B + ⊕ = + = + = +

P G Co,0 Co,1 P G Ci,1

VDD VDD

1

P G P G P G A B A B P G

1 1

Example – Propagate, A and B Unequal

( ) ( )

C

AB C AB C G P A C B A B + ⊕ = + = + = +

P G Co,0 Co,1 P G Ci,1

VDD VDD

1 Ci,1 1 Ci,1

P G P G P G A B A B P G

1 1 1 1 1 1

SLIDE 7

7 Adder using “P and G”

Even Odd

XOR in Transmission Gate Full Adder

Delete, Propagate, Generate, D A B P A B G AB = = ⊕ =

B A B A B

Transmission Gate XOR

P A B = ⊕

B B

Transmission Gate Full Adder

B A B A

P

S C

A B C P

1 1 1 1

S

O

C

B A B A

P

B B

O

C

S

B C C

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

B

1 1 1

Only 16 transistors! (24 if we count the inversion of B, S, and CO)

np-CMOS Adder

Single stage

C

VDD

φ A B

VDD

C A B φ N-Block C

VDD

φ

peration

Very low load in critical path i.e. Very fast

C B A B A

VDD

φ

VDD

φ C B S0 φ φ P-Block N-Block Co,0 Ci,1

VDD

φ φ

17 Trans.

Co,1 φ φ φ C B A C C B B B A A A P-Block S0 Ci,0 φ

SLIDE 8

8 NORA

Only Carry Path Shown

VDD VDD

Co,1 φ φ B B A A Ci,0 B A B A

VDD

Co,0 φ φ φ φ φ φ φ φ

Inverting elements between registers!!!

Carry Bypass

A B C i S C o 0 Delete 1 1 0 Delete 1 1 0 Propagate 1 1 1 Propagate 1 1 0 P t

A B

1 1 0 Propagate 1 1 1 Propagate 1 1 1 Generate 1 1 1 1 1 Generate

S Ci Co FA

i

A B C C ≠ = give Bypass carry if P=1 P A B = ⊕ Propagate,

i

A B C C = give independent of

Carry Bypass

A0 B0 A1 B1 P0 P1

,1 ,0 1 1

i

C C A B A B = ≠ ≠ if and

FA FA Ci,0 Co,0 Co,1

,1 ,0 1 ,1 ,0

i
i

C C P P C C = that is if

therwise

independent of Bypass carry when P0 P1

Carry Bypass Adder

G1 G3 G0 G2 P1 P3 P0 P2 P1 P3 P0 P2 C0 C2 S1 S3 S0 S2

1 3 2 1 3 2

FA FA FA FA

C1 C3 Co3

P1 P3 P0 P2 Bypass if = 1

Otherwise Co3 independent of C0

SLIDE 9

9 Carry Bypass Adder

If A = B in at least one adder cell ⇒ Co not dependent on Ci

Setup S9 S11 S8 S10

FA FA FA FA

Setup S13 S15 S12 S14

FA FA FA FA

S5 S7 S4 S6

FA FA FA FA

Setup S1 S3 S0 S2

FA FA FA FA

Setup

If A ≠ B in all adders ⇒ Bypass Carry

Carry Ripple v.s. Carry Bypass

tadder

N = 4-8

N

Carry Select

Setup

FA FA FA FA FA FA FA FA

C C

"0" "1"

Sum Gen. S1 S3 S0 S2 Co,k+3 Ci,k

Carry Select: Critical Path

Setup Setup Setup Setup

FA FA FA FA FA FA FA FA

Co,3 Ci,0 1

FA FA FA FA FA FA FA FA

Co,7 1

FA FA FA FA FA FA FA FA

Co,11 1

FA FA FA FA FA FA FA FA

1

Large area (two adders not needed in first stage)

Sum Gen. Sum Gen. Sum Gen. Sum Gen. S9 S11 S8 S10 S13 S15 S12 S14 S5 S7 S4 S6 S1 S3 S0 S2

SLIDE 10

10 Linear Carry Select

FA FA FA FA

Setup

FA FA FA FA

Setup

FA FA FA FA

Setup

FA FA FA FA

Setup

FA FA FA FA FA FA FA FA

Co,3 Ci,0 1

FA FA FA FA FA FA FA FA

Co,7 1

FA FA FA FA FA FA FA FA

Co,11 1

FA FA FA FA FA FA FA FA

1

The same number of bits in each stage

Sum Gen. Sum Gen. Sum Gen. Sum Gen. S9 S11 S8 S10 S13 S15 S12 S14 S5 S7 S4 S6 S1 S3 S0 S2

Square Root Carry Select

Setup Setup

Setup

FA FA FA

Co,1 Ci,0 1

FA FA FA FA FA FA

Co,4 1

FA FA FA FA FA FA FA FA

Co,8 1

FA FA FA FA FA FA FA FA

1

FA FA FA

Sum Sum Sum Gen. Sum Gen. S9 S11 S8 S10 S13 S12 S5 S7 S4 S6 S1 S3 S0 S2

Adder Delays - Comparison

tadder

Ripple Square Root Linear

N

Square Root

Carry Look Ahead (CLA)

i i

P

c G b) (a c ab c + = + + =

1 i,0 1 1 1

,0

1

,1

i,0

,0

i i

P

P P P P G P G G P G P P c P G G P c G c P c G c ) ( + + = + = + =

2 1 i,0 2 1 2 1 2 2

,1

2

,2

P P P c P P G P G G P c G c + + + = + =

SLIDE 11

11 Carry Look Ahead

1 i,0 1 1 1

,0

1

,1

i,0

,0

P P C P G G P C G C P C G C + + = + = + =

3 2 1 i,0 3 2 1 3 2 1 3 2 3

,2

3

,3

2 1 i,0 2 1 2 1 2 2

,1

2

,2

P P P P C P P P G P P G P G G P3 C G C P P P C P P G P G G P C G C + + + + = + = + + + = + =

Co,0 Co,3 Co,2 Co,1

Two’s complement conversion

Often done when adding two numbers

A B A A A B B B I 1 A0 B0 A3 A2 A1 B3 B2 B1 Inverse

f B

FA FA FA FA S0 S3 S2 S1 Added at LSB position

Adder/ Subtractor

A0 B0 A3 A2 A1 B3 B2 B1 CTRL FA FA FA FA

CTRL B XOR 0 0 0 0 1 1 1 0 1 1 1 0

Bit-Serial Serial Addition

a

Digit-Serial

i

a

i

b

1 + i

a

1 + i

b

2 + i

a b

i

s

1 + i

s

2 + i

s

i

cout

1 + i

cout

i

a

i

b

i

s

i

cout

Δ

b) a)

Δ

2 + i

b

2 + i

cout

SLIDE 12

12 Binary Multiplication Unsigned

N 1 1 1 * 1 1 1 1 1 1 1 1 1 11 42 Partial Products M N + 1 1 1 1 1 1 1 1 1 0 462 N+ M-1

Sign Extension in Two’s Complement

Example:

16+2 -32+16+2

10010 110010 1110010 11110010 00010 000010 0000010 00000010 = = = = = = = =

Binary multiplication

1 1 1

22

*

11 10 1 1

1 1 1

5

1 1 1 1 1 1

Two´ s Complement

(Better methods exist)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1

110

Array Multiplier

xi xi yj yj

Basic cells

FA HA

Co Ci S S Co x3 x1 x0 x2 yj

HA FA FA HA

Partial Product

SLIDE 13

13 Array Multiplier

HA FA FA HA

y1 y0 x3 x1 x0 x2 x3 x1 x0 x2

HA FA FA HA FA FA FA HA

y2 y3 x3 x1 x0 x2 x3 x1 x0 x2

FA FA FA HA

y3 z3 z1 z0 z2 z5 z4 z6

Array Multiplier: Critical Path

HA FA FA HA FA FA FA HA FA FA FA HA

Carry Save Multiplier

Only one Only one critical path One extra adder

HA FA FA FA HA HA HA HA

Suitable for CLA

FA FA FA HA FA FA HA HA

Multiplier Floorplan

HA HA HA HA FA FA FA HA FA FA FA HA FA FA FA HA FA FA HA HA

SLIDE 14

14 Booth´ s Modified Algorithm

Code the binary number

{0,1} { 2, 1,0,1,2}

i i

x y ∈ ∈ − −

To a five digit number

{ , , , , }

i

y

By using 3 binary bits

Booth´ s Modified Algorithm

1 1 2

2 2 0 1 Example 6

k i k i i i k

X x x x { , } k

− − = −

= − × + × ∈ =

∑

5 4 3 2 1 5 4 3 3 2 1 1 1 1 1

Example 6 32 16 8 4 2 16 2 4 2 2 2

i i i i

k

X x x x x x x X ( x x x ) ( x x x ) ( x x ) If y x x x x

+

= = − + + + + + = − + + + − + + + − + + = − + +

1 1 4 2 2 2 2

2 16 4 2 1 0 1 2 2 n, i even 4

i i i i- i i i i i k i k i

If y x x x X Y y y y y {- ,- , , , } Y y Y y

+ × = − =

+ + = = + + ∈ = × ⇒ =

∑

1 −

∑

Booth´ s Modified Algorithm

Examples:

i i 1 i i-1

y 2x x x

+

= − + +

Examples:

xi+1 xi xi-1 yi 1 1 1 1 1 1 2

X 01 11 01 10 (0) Y 02 01 02 02 X 00 10 01 11 (0) Y 01 02 02 01 = ⇒ = = ⇒ =

1

2

1 1

1

1 1

1

1 1 1

X 10 11 10 10 (0) Y 01 00 01 02 = ⇒ =

There will always be at least one “0” in each pair

Booth´ s Modified Algorithm

0 1 0 1 5 0 1 0 1 5 x 0 1 1 1 7 x 2 1 7 x 0 1 1 1 7 x 2

1

7 0 1 0 1 1 x 5 1 1 1 1 1 0 1 1

5

0 1 0 1 2 x 5 + 0 1 0 1 2 x 4 x 5 0 1 0 1 4 x 5 0 0 1 0 0 0 1 1 + 0 0 0 0 0 x 5 0 0 1 0 0 0 1 1

1 ⇒ two´ s complement conversion

2 ⇒ shift one step (multiply by two)

2 ⇒ two´ s complement conversion + shift

SLIDE 15

15 Booth´ s Modified Algorithm

yj-1 Xi+2 y Xi Xi+1

Booth Booth Booth Booth Booth Adder Adder Adder Adder

yj+1 yj

Coder Booth MUX MUX MUX MUX Booth Booth Booth Booth

1 × 2 ×

Adder Adder Adder Adder

yj+3 yj+2

Booth Coder Booth MUX Booth MUX Booth MUX Booth MUX