Border Control: Sandboxing Accelerators
- L. E. Olson, Jason Power, Mark. D. Hill and David A.Wood
University of Wisconsin-Madison Presented by: Yash Bhalgat, Arun Subramaniyan
Border Control: Sandboxing Accelerators L. E. Olson, Jason Power, - - PowerPoint PPT Presentation
Border Control: Sandboxing Accelerators L. E. Olson, Jason Power, Mark. D. Hill and David A.Wood University of Wisconsin-Madison Presented by : Yash Bhalgat, Arun Subramaniyan Key Id Ideas and goals Sharing memory between host and
University of Wisconsin-Madison Presented by: Yash Bhalgat, Arun Subramaniyan
accelerators without compromising on the performance?
Cryptographic accelerators, GPGPUs, accelerators for image processing, neural and approximate computing, database accelerators, user reconfigurable hardware, etc.
erroneously corrupting the OS data structures
attacker (e.g.: MIPS R4000)
Guess which website left this data in the GPU texture memory?
“Stealing Webpages Rendered on Your Browser by Exploiting GPU Vulnerabilities”, Lee et al. (Oakland ’14)
attacker’s perspective
Threat Vector: Protect host from incorrect or malicious accelerators that could perform Addressed Threats:
“Every hardware component of the system should operate using the least set of privileges necessary to complete the job.”
CPU $$ $$
Memory or Shared LLC
MMU TLB
Accel. Trusted data path Untrusted data path Address translation path Translation update path Accel.
Direct Physical Address
CPU $$ $$
Memory or Shared LLC
MMU TLB
Accel. Trusted data path Untrusted data path Address translation path Translation update path Accel.
Full IOMMU
Full IOMMU
Trusted data path Untrusted data path Address translation path Translation update path
Bypassable IOMMU
CPU $$
Memory or Shared LLC
$$
TLB
Accel. $$
TLB
Accel. $$
IOMMU
Trusted data path Untrusted data path Address translation path Translation update path CPU $$
Memory or Shared LLC
$$
TLB
Accel. $$
TLB
Accel. $$
IOMMU
Notify OS (terminate process/disable accelerator)
*From paper
CPU $$
Memory or Shared LLC
$$
TLB
Accel. $$
TLB
Accel. $$
IOMMU
R W
PPN N 1 .. 1MB for 16GB memory
CPU $$
Memory or Shared LLC
$$
TLB
Accel. $$
TLB
Accel. $$
IOMMU
IOMMU+ BCC
Takeaway: Average 0.48% performance overhead
Moderately-Threaded GPU
Highly-Threaded GPU
Takeaway: Average 0.15% performance overhead
accesses at low performance and area overheads (0.006% extra memory)
accelerators ? (> 100 IP blocks). The paper proposes 1 protection table per accelerator.
granularity (word, block..)? What are the challenges?
from malicious/buggy coherence messages ?