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Basic Steps for Execution Fetch an instruction from the instruction store Decode it What does this instruction do? Gather inputs From the register file From memory Perform the operation Write back the outputs To

  1. Basic Steps for Execution • Fetch an instruction from the instruction store • Decode it • What does this instruction do? • Gather inputs • From the register file • From memory • Perform the operation • Write back the outputs • To register file or memory • Determine the next instruction to execute 7

  2. The Processor Design Algorithm • Once you have an ISA… • Design/Draw the datapath • Identify and instantiate the hardware for your architectural state • Foreach instruction • Simulate the instruction • Add and connect the datapath elements it requires • Is it workable? If not, fix it. • Design the control • Foreach instruction • Simulate the instruction • What control lines do you need? • How will you compute their value? • Modify control accordingly • Is it workable? If not, fix it. • You’ve already done much of this in 141L. 8

  3. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  4. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  5. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  6. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  7. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  8. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  9. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  10. • Arithmetic; R-Type • Inst = Mem[PC] • REG[rd] = REG[rs] op REG[rt] • PC = PC + 4 bits 31:26 25:21 20:16 15:11 10:6 5:0 name op rs rt rd shamt funct # bits 6 5 5 5 5 6

  11. • ADDI; I-Type • PC = PC + 4 • REG[rd] = REG[rs] op SignExtImm bits 31:26 25:21 20:16 15:0 name op rs rt imm # bits 6 5 5 16 10

  12. • ADDI; I-Type • PC = PC + 4 • REG[rd] = REG[rs] op SignExtImm bits 31:26 25:21 20:16 15:0 name op rs rt imm # bits 6 5 5 16 10

  13. • Load Word • PC = PC + 4 • REG[rt] = MEM[signextendImm + REG[rs]] bits 31:26 25:21 20:16 15:0 name op rs rt immediate # bits 6 5 5 16 11

  14. • Load Word • PC = PC + 4 • REG[rt] = MEM[signextendImm + REG[rs]] bits 31:26 25:21 20:16 15:0 name op rs rt immediate # bits 6 5 5 16 11

  15. • Store Word • PC = PC + 4 • MEM[signextendImm + REG[rs]] = REG[rt] bits 31:26 25:21 20:16 15:0 name op rs rt immediate # bits 6 5 5 16 12

  16. • Store Word • PC = PC + 4 • MEM[signextendImm + REG[rs]] = REG[rt] bits 31:26 25:21 20:16 15:0 name op rs rt immediate # bits 6 5 5 16 12

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