BabyBEE Defining the Silicon Circuit Board CASPER Workshop August - - PowerPoint PPT Presentation

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BabyBEE Defining the Silicon Circuit Board CASPER Workshop August - - PowerPoint PPT Presentation

Apr 24, 2023 225 likes •405 views

BabyBEE Defining the Silicon Circuit Board CASPER Workshop August 4, 2008 Bob Conn CTO siXis Spin-out of Research Triangle Institute Started July 3, 2008 $5.2M MiniBee Alpha product already delivered BabyBEE available early

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SLIDE 1

BabyBEE

Defining the Silicon Circuit Board

CASPER Workshop

August 4, 2008 Bob Conn CTO

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SLIDE 2

2

siXis

  • Spin-out of Research Triangle Institute
  • Started July 3, 2008
  • $5.2M
  • MiniBee Alpha product already delivered
  • BabyBEE available early 2009
  • Derivative of BEE2
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SLIDE 3

3

BabyBEE

  • Started with BEE2 at BWRC
  • BabyBEE
  • Smaller
  • Faster
  • Cooler
  • Less expensive
  • Lower operating costs
  • Xilinx V5
  • Futures with CPUs, other FPGAs, RF, etc.
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SLIDE 4

4

SiCB vs. Multi-Chip Module vs. PCB

SICB MCM* PCB 2007* Board-to-board interconnect density 1600% 625% 100% Layers for interconnect to exit BGA 25% 63% 100% Pad pitch 24% 40% 100% Trace pitch (width plus space) 16% 32% 100% Via diameter (through substrate) 60% 90% 100% Microvia diameter (not through substrate) 13% 100% 100% Maximum substrate size 10% 20% 100% Functionality per unit area 10x 10x 1 Cost per unit functionality 41% 54% 100% Reliability Better Worse Average

*The Information Network, Internal RTI analysis

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SLIDE 5

5

MiniBEE

  • FR-4 based version of BabyBEE
  • Architectural verification
  • Early adopter software development platform

5” x 10” 22 layer FR-4 V5LX220

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SLIDE 6

6

BabyBEE

FPGA die Power SiCB Cooling

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SLIDE 7

7

32 FPGAs, 256 Memory Chips

BabyBEE = SiCB technology validating application

High performance reconfigurable computing Excellent application of the SiCB platform

  • Designs are scalable
  • FPGAs available as known (mostly) good die today
  • Rapidly developing market
  • High value placed on low power and small size

2” x 3 ½” x 3 ½”

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SLIDE 8

8

BabyBEE Architecture

W

V5LX110T

Z

V5LX110T

X

V5LX110T

Y

V5LX110T

1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory 1GB Memory CX4 16 channels CX4 16 channels CX4 16 channels CX4 16 channels

A Typical Small System I/O I/O

Torus Bus (red) Shared Bus (black) Local Bus

A C B D A C B D A C B D A C B D A C B D B V5LX220 A V5LX220 C V5LX220 D V5LX220 B V5LX220 A V5LX220 C V5LX220 D V5LX220 B V5LX220 A V5LX220 C V5LX220 D V5LX220 B V5LX220 A V5LX220 C V5LX220 D V5LX220

Compute Board

Ethernet Ethernet Ethernet Ethernet

I/O Board

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SLIDE 9

9

BabyBEE Advantages

  • Lower parasitic capacitances (and inductance)
  • Less need for bypassing
  • Vertical interconnect density 12:1
  • Horizontal wire density 12:1
  • Wires are RC, not LC
  • Termination resistors almost eliminated
  • Easier to design
  • FR4 already requires a microwave engineer
  • Increased I/O density on FPGAs because of smaller I/O drivers
  • Limited by package constraints today
  • I/O buffers can be smaller  6pF to 3pF
  • New chip designs
  • Alignment
  • Approximately 1mil for FR4 to 1 micron for SICB
  • Stacking memory – the wiring problem is minimum
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SLIDE 10

10

Desktop Brick

  • 4” x 6” x 8”
  • 0.35 TFlops (dp)
  • 30 TOps (16 bit)
  • 16 FPGAs
  • 16 GB memory
  • 50Gb/s I/O
  • < $100k
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SLIDE 11

11

The Cube

Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE Power distribution (copper) 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE I/O latency = 12ns 8x BabyBEE 8x BabyBEE 8x BabyBEE 8x BabyBEE

884mm. 720mm.

37 petaOps (16 bit int)

The Cube 27" x 34" x28" 8x8x8 < $100M 4096 BabyBEE Boards 16,384 FPGAs 18 TB memory 500kW 360 Tflops (dp) 37 petaOps #1 Supercomputer Maximum latency across The Cube < 20ns

Just for Fun

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SLIDE 12

12

BabyBEE Products

PCB Package Brick Cube

Size mm 80 x 100 x 10 100 x 100 x 50 1000x1000x1000 FPGAs 4 32 16,384 Memory 4GB 32GB 16 TB Power 150W +12v 1200W +48v 500kW +48v GP I/O 560 Serial I/O 40-80 channels more if needed

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SLIDE 13

13

  • Size is connector

limited

  • I/O: Expect 5Gb/s

per channel  6 BabyBEE I/O Modules

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SLIDE 14

14

BEE2 Through BabyBEE

BabyBEE

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SLIDE 15

15

Core Technology and Intellectual Property

Large-area SICBs attempted and failed 15 years ago

  • Reliability an issue > 1”x1”
  • Delamination/cracking occurred under routine thermal

cycling

  • Inadequate interconnect density
  • Known good die issue

BEECo’s technology allows reliable 4”x5” SICBs (min.)

  • Higher interconnect density, fewer signal layers
  • High aspect ratio through-silicon-vias technology
  • Mechanical re-enforcement (rivets)
  • Stress-relieving structures (spongy oxide and service

loops)

Eight patents filed, 16 disclosures

High aspect ratio vias Spongy oxide

10µ

SiO2 #1

LOW-K #1 52 51 55 SILICON SUBSTRATE COPPER 56 12µ

SILICON SUBSTRATE

SiO2 SiO2

LOW-K #2 LOW-K #1 COPPER 301 302 311 310 312

Service loops

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SLIDE 16

16

BabyBEE vs. MiniBEE

83mm 50mm

215mm

A B A B

10mm

100mm

21.24 31.42 21.24 31.42

FR4 PCB MiniBEE

0.7 TFlops (dp) 60TOps (16bit) 300 Gb/s I/O 8GB memory 800W

SICB BabyBEE

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SLIDE 17

17

MiniBEE I/O Board

CFG/STAT I/O B 36 A2C 74 74 Share D Share B 80 74 74 Share A Share C CX4 x5 80 64M x 32 64M x 32 64M x 32 64M x 32 74 Torus A 74 Torus C 74 Torus B 74 Torus D MEM1A MEM2A MEM1B MEM2B DDR2 DDR2 38 CFG/STAT B 38 38 38 38 38 CFG/STAT I/O A JTAG DDR2 DDR2 CX4 x5 8M x 36 MEM3A RLDRAM 64M x 32 MEM3B RLDRAM 74 74 74 74 73 73 RS232 Level Shift 20 B2C BOOT PROM SPI

A

V5FX130T 840 I/O

CLOCKS 125, 156 200, 333 MHz 64M x 32 64M x 32 MEM1C MEM2C DDR2 DDR2 72 72

B

V5FX130T 840 I/O

A2B 74

Ethernet PHY RJ-45

14 JTAG CFG/STAT D CFG/STAT C CFG/STAT A B6,8 B12,18 B11,13 B20,24 B25,29 B15,19 B23,27 B5 B1,2 B17,21

C

V5LX110 800 I/O

Unused B7,24 Clocks &LEDs B4 CLOCK 25 MHz B19 B38 B12 B17 B11 B13 B21,25 B18,26 B5 B6 B23

10/100

LEDS DBG HDR FAN CNTRL SYSACE 42 8 2 6 USB 2.0 CY7C6801 3A RTC JTAG 2