Asynchronous Arbitration Primitives for New Generation of Circuits - - PowerPoint PPT Presentation

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Asynchronous Arbitration Primitives for New Generation of Circuits - - PowerPoint PPT Presentation

Sep 23, 2023 31 likes •271 views

Asynchronous Arbitration Primitives for New Generation of Circuits and Systems Andrey Mokhov, Danil Sokolov, Victor Khomenko, Alex Yakovlev Newcastle University, UK Motivating example: toy buck converter under-voltage V_ref V_pmos gp_ack

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Asynchronous Arbitration Primitives for New Generation of Circuits and Systems

Andrey Mokhov, Danil Sokolov, Victor Khomenko, Alex Yakovlev Newcastle University, UK

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Motivating example: toy buck converter

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V_nmos V_pmos

R_load PMOS NMOS

gp_ack uv gn_ack gp gn

analog buck digital control

V_ref

under-voltage

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SLIDE 3

Motivating example: toy buck converter

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V_nmos V_pmos

R_load PMOS NMOS

gp_ack uv gn_ack gp gn

analog buck digital control

V_ref

under-voltage

clk

RTL synthesis

  • Synchronous implementation – requires synchronisers for asynchronous inputs
  • Synchronisers also sanitize hazardous / dirty inputs from analog environment
  • Reaction time – 3 clock cycles
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SLIDE 4

Motivating example: toy buck converter

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V_nmos V_pmos

R_load PMOS NMOS

gp_ack uv gn_ack gp gn

analog buck digital control

V_ref

under-voltage

sanitiser

speed-independent logic synthesis

  • Asynchronous implementation – natural for asynchronous inputs
  • Reaction time – several gate delays
  • Need to sanitise hazardous under-voltage input
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Asynchronous arbitration primitives

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  • Synchronisation
  • WAIT: synchronise with high level of hazardous input
  • RWAIT: WAIT that can be with released/cancellation
  • WAIT01: synchronise with hazardous rising edge
  • WAIT2: synchronise with both phases of a hazardous input
  • Decision-making
  • WAITX: arbitrate between two hazardous inputs
  • OM: merges two request-acknowledgement channels into one
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WAIT: synchronise handshake with high level of hazardous input

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D.Sokolov et.al. “Design and verification of speed-independent multiphase buck controller”, ASYNC, 2015.

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WAIT: synchronise handshake with high level of hazardous input

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D.Sokolov et.al. “Design and verification of speed-independent multiphase buck controller”, ASYNC, 2015.

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RWAIT: WAIT that can be released/cancelled

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RWAIT: WAIT that can be released/cancelled

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RWAIT: WAIT that can be released/cancelled

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WAIT01: synchronise handshake with rising edge of hazardous input

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WAIT01: synchronise handshake with rising edge of hazardous input

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WAIT2: synchronise handshake with both phases of hazardous input

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WAIT2: synchronise handshake with both phases of hazardous input

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WAITX: arbitrate between two hazardous inputs

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V.Khomenko et.al. “WAITX: An arbiter for non-persistent signals”, ASYNC, 2017.

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WAITX: arbitrate between two hazardous inputs

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V.Khomenko et.al. “WAITX: An arbiter for non-persistent signals”, ASYNC, 2017.

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WAITX: arbitrate between two hazardous inputs

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MUTEX

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OM: merge two handshake channels into one

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A.Mokhov et.al. “Opportunistic merge element”, ASYNC, 2015.

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OM: merge two handshake channels into one

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r1 r2 r1 r2 r1 r2 ra ra ra a1 a2 a1 a2 r1 r2 r1 r2 r1 r2 ra ra ra a1 a2 a1 a2 {a1,a2}

Standard merge Opportunistic merge

A.Mokhov et.al. “Opportunistic merge element”, ASYNC, 2015.

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OM: merge two handshake channels into one

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A.Mokhov et.al. “Opportunistic merge element”, ASYNC, 2015.

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Application example: multiphase buck converter

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R_load

V_nmos V_pmos V_nmos V_pmos

analog buck

PMOS NMOS PMOS[N] NMOS[N]

digital

  • c

zc

  • cN

uv zcN gn_ackN gn_ack gp gp_ack gn gp_ackN gpN gnN hl

  • ver-current

I_0 (I_neg) I_max (I_0) I_max (I_0) I_0 (I_neg) V_ref

zero-crossing under-voltage

V_min

high-load

V_max

  • ver-voltage
  • v

basic converter

control

multiphase converter

  • Phases – pairs of power regulating transistors
  • Each phase operates as a basic buck
  • Phases are activated sequentially
  • Active phases may overlap
  • Many operating modes
  • under-voltage (UV)
  • ver-current (OC)
  • zero-crossing (ZC)
  • ver-voltage (OV)
  • high-load (HL)
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SLIDE 22

Application example: multiphase buck converter

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  • asynchronous arbitration primitives
  • synthesised speed-independent components
  • external delay elements
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SLIDE 23

Application example: multiphase buck converter

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  • Benefits over conventional synchronous design with synchronisers
  • No synchronisation failures
  • Quick response time (few gate delays)
  • Reaction time can be traded off for smaller coils
  • Lower voltage ripple and peak current

D.Sokolov et.al. “Benefits of async. control for analog electronics: multiphase buck case study”, DATE, 2017.

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Conclusions

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  • Library of asynchronous arbitration primitives

https://github.com/workcraft/arbitration-primitives

  • Low-latency synchronisation and decision-making
  • Developed and formally verified in WORKCRAFT (workcraft.org)
  • Building blocks for applications that require:
  • Efficient synchronisation between clock and voltage domains
  • Sanitising ‘dirty’ signals from analog environment
  • Demonstrated benefits in the area of power converters