Arkadiusz Bukowiec Faculty of Electrical Engineering, Computer - - PowerPoint PPT Presentation

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Arkadiusz Bukowiec Faculty of Electrical Engineering, Computer - - PowerPoint PPT Presentation

Apr 11, 2024 141 likes •424 views

13th - 14th December 2012 Liverpool, United Kingdom Arkadiusz Bukowiec Faculty of Electrical Engineering, Computer Science and Telecommunications Institute of Computer Engineering and Electronics University of Zielona Gra P OLAND

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Arkadiusz Bukowiec

Faculty of Electrical Engineering, Computer Science and Telecommunications Institute of Computer Engineering and Electronics University of Zielona Góra POLAND

13th - 14th December 2012 Liverpool, United Kingdom

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 Introduction  Petri Net

 Interpreted  Colored

 Distributed Application Specific

Logic Controller

 Architecture  Synthesis

 Conclusion 2

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11

t1 t2 t3 t4 t5 t6 t7 t8 t9 XN1 XF1 XN2 XF1 XF2 XF4 XF3 YT1 YV1 YT2 YV1 YV2 YV3 YM

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11

t1 t2 t3 t4 t5 t6 t7 t8 t9

 P – set of places  T – set of transitions  F – set of arcs  M0 – set of initial marking

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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7  Extension for information

exchange

 Additional binary signals

 X – set of input variables  Y – set of output variables  Z – set of internal variables

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11

t1 t2 t3 t4 t5 t6 t7 t8 t9 XN1 XF1 XN2 XF1 XF2 XF4 XF3 YT1 YV1 YT2 YV1 YV2 YV3 YM

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8  Colors assigned to places and

transitions

 Each color determine

 State-machine subnet  Sequentiaql process

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

50% 50% 50% 50% 50% 50% 50% 50% 50% 50%

P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11

t1 t2 t3 t4 t5 t6 t7 t8 t9 XN1 XF1 XN2 XF1 XF2 XF4 XF3 YT1 YV1 YT2 YV1 YV2 YV3 YM

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SLIDE 9

Architecture

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SLIDE 10 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%

P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11

t1 t2 t3 t4 t5 t6 t7 t8 t9 XN1 XF1 XN2 XF1 XF2 XF4 XF3 YT1 YV1 YT2 YV1 YV2 YV3 YM

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 No global clock signal  Independent, local clock signals for each

subcicuit

 Different methods of communication

(synchronization)

 Handshake-based  FIFO-based  Controller-based  Lookup-based  Buffer-based

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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P2 P3 P7 P8

SMN 1 SMN 2 SMN 3

P1 P2 P4 P5 P6

t1 t2 t3 t4 t5 XN1 XF1 XN2 XF1 YT1 YV1 YT2 YV1

P3 P7 P10 P11

t5 t6 t7 t8 XF1 XF4 XF3 YV3 YM t2

MP1 P9 P8

t6 t8 t9 XF2 XF3 YV2

MP2

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An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

CC1 RG1

Y D1 X

Y1 CC2 RG2 CCI RGI

D2 DI Q1 Q2 QI

Y2 YI

Y1 Y2 YI Z YZ

1

YZ

2

YZ

I Q Q Q Y Y Y YZ YZ YZ Q Q Q D D D D D D Q Q Q X X X XZ XZ XZ

SMNI SMN2 SMN1 X1 X2 XI XZ

1

XZ

2

XZ

I

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Synthesis method

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 Decomposition into state machime subnets  Constructing the set of synchronizing variables  Places encoding  Forming conjunctions and formulas  Creating decoder memory blocks  Forming logic circuit 15

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 All places colored by first color creates first

state machine subnet

 All the subsequent subnets are created in a

similar way, except that all the sequences of places, which have already been placed in one

  • f the previously created subnets are replaced

by a macroplace

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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P1 P2 P4 P5 P6

t1 t2 t3 t4 t5 XN1 XF1 XN2 XF1 YT1 YV1 YT2 YV1

P3 P7 P10 P11

t5 t6 t7 t8 XF1 XF4 XF3 YV3 YM t2

MP1 P9 P8

t6 t8 t9 XF2 XF3 YV2

MP2

50% 50% 50% 50% 50% 50% 50% 50% 50% 50%

P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11

t1 t2 t3 t4 t5 t6 t7 t8 t9 XN1 XF1 XN2 XF1 XF2 XF4 XF3 YT1 YV1 YT2 YV1 YV2 YV3 YM

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 If a transition belongs to more that one state

machine subnet, then transition input place in each subnet have to generate additional synchronization signal

 The fire condition of this transition in each

subnet have to be extended by logical conjunction of signals generated by other subnets

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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P1 P2 P4 P5 P6

t1 t2 t3 t4 t5 XN1 XF1 XN2 XF1 YT1 YV1 YT2 YV1

P3 P7 P10 P11

t5 t6 t7 t8 XF1 XF4 XF3 YV3 YM t2

MP1

P9 P8

t6 t8 t9 XF2 XF3 YV2

MP2

YP2 YP3 XP2 XP3 YP7 YP8 XP7 XP8

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 Minimum length code  Separately for each subnet  The place that belongs to initial marking

receive code equal to 0

 If there is no such place the code equal to 0 is

assigned to a double macro place of such place

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 Separately for each subnet  Conjunction describing place is formed with

literals from the code of this place

 Conjunction related to a transition is formed

using the conjunction of its input places and its guard condition

 Conjunction describing place hold condition is

formed as conjunction of this place conjunction and negated disjunction of all conjunctions of its output places

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 Separately for each subnet  Created based on D flip-flop equation  Denoted as

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 Separately for each subnet  Described as

 Truth table  Logic equations

 Code of place forms address  Output variables forms word  Only output variables controlled by considered

subnet are taken

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 Each subnet described as separate

module

 Described in HDL

 Combinational circuit is described with the

use of continues assignments

 Register memory described as D flip-flop  Decoder described as process with case

statement

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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 Petri net allows an easy description of parallel

processes

 GALS architecture allows distribution of the

system

 The synchronization is made via buffers  Proposed architecture and synthesis method is

dedicated for FPGA devices

An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets Arkadiusz Bukowiec

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