An example of a research compiler Simone Campanoni - - PowerPoint PPT Presentation

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An example of a research compiler Simone Campanoni - - PowerPoint PPT Presentation

Jan 05, 2023 16 likes •472 views

An example of a research compiler Simone Campanoni simonec@eecs.northwestern.edu Sequential programs are not accelerating like they used to Performance (log scale) Performance gap Core frequency scaling Multicore era Sequential program

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An example of a research compiler

Simone Campanoni simonec@eecs.northwestern.edu

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Core frequency scaling

Sequential programs are not accelerating like they used to

1992 2004 Performance (log scale) Multicore era Performance gap

Sequential program running on a platform

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Single application: Not enough explicit parallelism

  • Developing parallel code is hard
  • Sequentially-designed code is still ubiquitous

Multiple applications: Only a few CPU-intensive applications running concurrently in client devices

Multicores are underutilized

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Parallelizing compiler: Exploit unused cores to accelerate sequential programs

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Numerical programs

Non-numerical programs Non-numerical programs need to be parallelized

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99% of time is spent in loops

Parallelize loops to parallelize a program

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Time

Outermost loops

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work() work() work()

DOALL parallelism

Iteration 0 Iteration 1 Iteration 2 Time

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c=f(c) d=f(d) work()

DOACROSS parallelism

c=f(c) d=f(d) work() c=f(c) d=f(d) work()

Sequential segment Parallel segment Time

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c=f(c) d=f(d) work() c=f(c) d=f(d) work() c=f(c) d=f(d) work()

HELIX: DOACROSS for multicore

[Campanoni et al, CGO 2012, Campanoni et al, DAC 2012, Campanoni et al, IEEE Micro 2012]

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c=f(c) d=f(d) work()

HELIX: DOACROSS for multicore

[Campanoni et al, CGO 2012, Campanoni et al, DAC 2012, Campanoni et al, IEEE Micro 2012]

c=f(c) d=f(d) work() c=f(c) d=f(d) work()

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c=f(c) d=f(d) work(x)

HELIX: DOACROSS for multicore

[Campanoni et al, CGO 2012, Campanoni et al, DAC 2012, Campanoni et al, IEEE Micro 2012]

c=f(c) d=f(d) work() c=f(c) d=f(d) work()

Seq. Segment 0 Seq. Segment 1 Wait 0 Wait 1 Signal 0 Signal 1

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HELIX: DOACROSS for multicore

[Campanoni et al, CGO 2012, Campanoni et al, DAC 2012, Campanoni et al, IEEE Micro 2012]

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HELIX: DOACROSS for multicore

[Campanoni et al, CGO 2012, Campanoni et al, DAC 2012, Campanoni et al, IEEE Micro 2012]

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99% of time is spent in loops

Parallelize loops to parallelize a program

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Time

Innermost loops Outermost loops

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Parallelize loops to parallelize a program

Outermost loops

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Innermost loops Coverage Communication Ease of analysis HELIX

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HELIX: DOACROSS for multicore

[Campanoni et al, CGO 2012, Campanoni et al, DAC 2012, Campanoni et al, IEEE Micro 2012]

Speedup SPEC INT baseline ICC, Microsoft Visual Studio,DOACROSS HELIX

4-core Intel Nehalem

4 1 16 Innermost loops Coverage Communication Easy of analysis HELIX Outermost loops

HELIX-RC HELIX-UP

Small Loop Parallelism

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Outline

Small Loop Parallelism and HELIX HELIX-RC: Architecture/Compiler Co-Design HELIX-UP: Unleash Parallelization

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[ISCA 2014] [CGO 2015] [CGO 2012 DAC 2012, IEEE Micro 2012]

Communication

HELIX Small loops

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SLP challenge: short loop iterations

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Clock cycles Duration of loop iteration (cycles)

SPEC CPU Int benchmarks

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SLP challenge: short loop iterations

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Clock cycles Duration of loop iteration (cycles)

SPEC CPU Int benchmarks

90

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SLP challenge: short loop iterations

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Clock cycles Duration of loop iteration (cycles) Adjacent core communication latency

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Seq. Segment 0 Seq. Segment 1 Wait 0 Wait 1 Signal 0 Signal 1

A compiler-architecture co-design to efficiently execute short iterations

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Compiler

  • Identify latency-critical code in each small loop
  • Code that generates shared data
  • Expose information to the architecture
  • Reduce the communication latency
  • n the critical path

Architecture: Ring Cache

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… Load Y …

  • Iter. 1

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Light-weight enhancement of today’s multicore architecture

Core 0 Core 1 Core 3 Core 2 DL1 DL1 DL1 DL1 Last level cache Ring node Ring node Ring node Ring node

Store X, 1 Store Y, 1

  • Iter. 0

Store Y, 1

  • Iter. 2

Store Y, 1

  • Iter. 3

Store X, 1 Load X

75 – 260 cycles!

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Core 0 Core 1 Ring node Ring node Ring node Ring node

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Light-weight enhancement of today’s multicore architecture

… Wait 0 Load Y …

  • Iter. 1

Store X, 1 Wait 0 Store Y, 1 Signal 0

  • Iter. 0
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98% hit rate

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The importance of HELIX-RC

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Non-numerical programs Numerical programs

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The importance of HELIX-RC

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Non-numerical programs Numerical programs

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Small Loop Parallelism and HELIX HELIX-RC: Architecture/Compiler Co-Design HELIX-UP: Unleash Parallelization

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[ISCA 2014] [CGO 2015] [CGO 2012 DAC 2012, IEEE Micro 2012]

Communication

HELIX Small loops

Outline

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HELIX and its limitations

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Thread 0 Thread 1 Thread 2 Thread 3

Data Data Data Iteration 0 Iteration 1 Iteration 2

Performance:

  • Lower than you would like
  • Inconsistent across architectures
  • Sensitive to

dependence analysis accuracy

What can we do to improve it?

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4 Cores 1.68 2.77 2.31 1.61 1.19 Nehalem Bulldozer Haswell 79% accuracy 78% accuracy

50% 80%

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Opportunity: relax program semantics

  • Some workloads tolerate output distortion
  • Output distortion is workload-dependent

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Relaxing transformations remove performance bottlenecks

  • Sequential bottleneck

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Inst 1 Inst 2 Inst 3 Inst 4 Inst 3 Inst 4 Inst 3 Inst 4

Dep

Thread 1 Thread 2 Thread 3

Inst 1 Inst 2 Inst 1 Inst 2 Speedup

Sequential segment

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Relaxing transformations remove performance bottlenecks

  • Sequential bottleneck
  • Communication bottleneck
  • Data locality bottleneck

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Relaxing transformations remove performance bottlenecks

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No relaxing transformations Relaxing transformation 1 Relaxing transformation 2 … Relaxing transformation k Max output distortion Max performance No output distortion Baseline performance

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Design space of HELIX-UP

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Code region 2 Code region 1

  • Performance
  • Energy saved
  • Output distortion

1) User provides output distortion limits 2) System finds the best configuration 3) Run parallelized code with that configuration

Apply relaxing transformation 3 to code region 1 Apply relaxing transformation 5 to code region 2

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Pruning the design space

Empirical observation: Transforming a code region affects only the loop it belongs to 50 loops, 2 code regions per loop 2 transformations per code region Complete space = 2100 Pruned space = 50 * (22) = 200

How well does HELIX-UP perform?

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HELIX: no relaxing transformations

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Nehalem 6 cores 2 threads per core

HELIX-UP unblocks extra parallelism with small output distortions

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HELIX-UP unblocks extra parallelism with small output distortions

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Nehalem 6 cores 2 threads per core

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Performance/distortion tradeoff

%

256.bzip2

HELIX

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Run time code tuning

  • Static HELIX-UP decides

how to transform the code based on profile data averaged over inputs

  • The runtime reacts to transient bottlenecks

by adjusting code accordingly

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Adapting code at run time unlocks more parallelism

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256.bzip2

%

HELIX

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HELIX-UP improves more than just performance

  • Robustness to DDG inaccuracies
  • Consistent performance

across platforms

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Relaxed transformations to be robust to DDG inaccuracies

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Increasing DDG inaccuracies leads to lower performance

No impact

  • n HELIX-UP

HELIX HELIX-UP

256.bzip2

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Relaxed transformations for consistent performance

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Increasing communication latency

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Small Loop Parallelism and HELIX

  • Parallelism hides in small loops

HELIX-RC: Architecture/Compiler Co-Design

  • Irregular programs require low latency

HELIX-UP: Unleash Parallelization

  • Tolerating distortions boosts parallelization

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Thank you!

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Small Loop Parallelism and HELIX

  • Parallelism hides in small loops

HELIX-RC: Architecture/Compiler Co-Design

  • Irregular programs require low latency

HELIX-UP: Unleash Parallelization

  • Tolerating distortions boosts parallelization

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