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Jan 16, 2024 109 likes •310 views

An Efficient and Effective Detailed Placement Algorithm White-paper by: Min Pan, Natarajan Viswanathan and Chris Chu Department of Electrical and Computer Engineering Iowa State University, Ames, IA 50011 Email: panmin, nataraj, cnchu

SLIDE 1

White-paper by: Min Pan, Natarajan Viswanathan and Chris Chu

Department of Electrical and Computer Engineering Iowa State University, Ames, IA 50011 Email: panmin, nataraj, cnchu @iastate.edu

Implemented by: Andronikidis Anastasios, Gaki Styliani and Ioannidis Stavros

Department of Computer and Comunication Engineering University of Thessaly, Greece

An Efficient and Effective Detailed Placement Algorithm

SLIDE 2

FastDP detailed placer

Improves the wire length of a legalized

placement

Moves the cells toward their optimal region
Result is also legalized

SLIDE 3

FastDP techniques

Global swapping
Vertical swapping
Local re-ordering
Single-segment clustering

SLIDE 4

Global Swapping

Identifies a good pair
f cells to swap

globally based on their optimal positions while all

ther cells are fixed

SLIDE 5

Vertical Swapping

Moves cells vertically toward their optimal

region

– Moves up and down by one row

Increases the possibility for a good global

swap

Faster and more flexible than global swapping

SLIDE 6

Local re-ordering

For every n consecutive cells within a

segment it chooses the left-right ordering that results the best wirelength

For a window of n cells there are n! possible
rderings, so n=3 is a good choice

SLIDE 7

Single-segment clustering

Places the cells (clusters) within a segment to

their optimal region's center

Merges possibly overlapping clusters and re-

places

Results a legalized placement

SLIDE 8

S400

SLIDE 9

S400 after swaps

SLIDE 10

S400 final

SLIDE 11

Expirements

Tested on 21 ISCAS legalized circuits
Benchmarks consist of standard cells only
Whitespace ~10%

SLIDE 12

Expiremental results

Benchmark Wire length improvement Runtime (sec) S208 42,3% <1 S298 34,6% <1 S344 42,9% <1 S349 37,0% <1 S382 35,1% <1 S386 42,6% <1 S400 34,2% <1 S420 42,1% <1 S444 34,7% <1 S510 48,1% 1 S526 35,3% <1 Benchmark Wire length improvement Runtime (sec) S641 33,0% 1 S713 33,2% 1 S820 44,0% 1 S832 49,9% 2 S838 43,4% 3 S953 49,1% 4 S1196 49,7% 9 S1423 45,8% 18 S1488 52,6% 7 S1494 51,6% 10 AVERAGE: 42,0%

SLIDE 13

WL Improvement over iterations

1 2 3 4 5 6 7 8 9 10 5 10 15 20 25 30 35 S208 S400 S641 S820 S1196

Iteration Wire Length Improvement (%)

SLIDE 14

Distance Improvement over iterations

1 2 3 4 5 6 7 8 9 10 0,9 0,95 1 1,05 1,1 1,15 1,2 1,25 1,3 1,35 1,4

Average cell distance from their optimal region

S400

Iteration Distance (in standard row height)

SLIDE 15

Area of Vertical Swapping

0,25 0,5 0,75 1 1,25 1,5 20 40 60 80 100 120 Global Swaps Vertical Swaps

Vertical Swap Factor Swaps

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Congestion-based approach

1 2 3 4 5 6 7 8 9 10 50 100 150 200 250

Increasing Core Area Width by 1% to 10%

Vertical Swaps between cells of different size Vertical Swaps between cells of same size Global Swaps between cells of different size Global Swaps between cells of same size

Core Area Width Increase (%) Swaps

SLIDE 17

Congestion-based approach

1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40

Increasing core area width by 1% to 10%

S400

Core Area Width Increase (%) Wire Length Improvement (%)

SLIDE 18

Profiling

SLIDE 19

Future work

Support macro blocks
Support GSRC placement format

(filetypes: .aux, .pl, .scl, .nodes, .nets, .wts).

Allow net-weighting