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May 22, 2023 247 likes •297 views

Digital IC Design Static CMOS V DD Chapter 6 p Pull-Up Net ll PUN PMOS Only l Combinational Logic Pull-Down Net PDN NMOS Only GND Continued Contin ed PUN and PDN are Dual Networks Example, Euler paths Propagation delay analysis

slide-1
SLIDE 1

1

Chapter 6

Digital IC Design

p Combinational Logic Contin ed Continued

Static CMOS

VDD

l ll NMOS Only PUN

GND

PDN PMOS Only Pull-Up Net Pull-Down Net

PUN and PDN are Dual Networks

Example, Euler paths

AB CD +

VDD VDD

One strip for each path

VDD

D B A C

DD

B B C D C A

ABCD

f

+ ABCD

f

+

Arrow end Arrow start

GND

A D

Propagation delay analysis

The switch model is attractive for manual calculations on complex gates Fix value on Req is a reasonable approximation. Which value? An average value over different regions:

( ) ( / 2)

  • 2

OUT DD OUT DD

n V V n V V eq n

R R R

= =

+ = =

( ) ( /2)

  • 2

2

OUT DD OUT DD

q DS DS D D V V V V eq n

V V I I R

= =

⎡ ⎤ ⎡ ⎤ + ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ =

slide-2
SLIDE 2

2

Example

( ) ( / 2)

OUT DD OUT DD

DS DS D D V V V V

V V I I R

= =

⎡ ⎤ ⎡ ⎤ + ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ =

Req-p 3V

2

eq n

R

−

300 400 500 600 700

ID [uA]

VGS=3

  • 100
  • 50
  • 0.5
  • 1
  • 1.5
  • 2
  • 2.5
  • 3

VDS

3/600μ = 5kΩ 1.5/500μ 3/200μ = 15kΩ 1.5/180μ = 8.4kΩ

Req-n

100 200 300 0.5 1 1.5 2 2.5 3

VDS

  • 250
  • 200
  • 150

ID [uA]

VGS=-3

μ = 3kΩ

Req-n = (3+ 5)/ 2 = 4kΩ Req-p = (15+ 8.4)/ 2 = 11.7kΩ See also equation 3.43

Analysis of Propagation Delay

Three cases

Req-p Req-p

  • 1. Pull up of one PMOS, Worst case

t pLH = 0.69RpCL

  • 2. Pull up of two PMOS at the same time

t pLH = 0.69(Rp / 2)CL

  • 3. Pull down of NMOS

t 0 69(2R )C B

q p q p

Req-n CL A A B t pHL = 0.69(2Rn)CL Req-n

NAND Scale Factor

W W L R 1 ∝ ∝

R proportional to one over the width:

B A tot

L L L + =

' K

For stacked (series) transistors, total length is double Lower hole mobility, in PMOS gives

A B

' K 3 ' ' ≈

p n

K K

Never change the length (except for pseudo-NMOS) Choose the one with lowest total width = smaller area and C

5 . 3 ' ' ≈

p n

K K

(Long Channel) (Short Channel)

Scale Factor for Worst Case

1 1

A B

Long Channel Assuming

Wp ≈ 3Wn

2 * 3 = 6

A

3 3

A B B

2 2

CL A

NAND

CL

2 * 3 = 6 1 1

B B A

NOR

B

2 * 1 = 2 2 * 1 = 2

CL A

NAND

Factor for stacked transistors

NAND

For stacked and low hole mobility For stacked and low hole mobility

(3.5 for short channel)

NOR NAND

slide-3
SLIDE 3

3

Problem 2

W/L = 2/0.35 kn’/kp’ = 3

a) Dimension worst case to be as balanced inverter. b) Express lowest resistance in terms of total resistance, R, if X = 1

A V

DD

D B D C A F E C B X E F

Problem 2 - Soultion