AScalable,NonblockingApproachto TransactionalMemory JaredCasper - - PowerPoint PPT Presentation

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a scalable non blocking approach to transactional memory
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AScalable,NonblockingApproachto TransactionalMemory JaredCasper - - PowerPoint PPT Presentation

Nov 24, 2022 24 likes •294 views

AScalable,NonblockingApproachto TransactionalMemory JaredCasper HassanChafi BrianD.Carlstrom AustenMcDonald WoongkiBaek ChiCaoMinh ChristosKozyrakisKunleOlukotun

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SLIDE 1
  • AScalable,NonblockingApproachto

TransactionalMemory

HassanChafi AustenMcDonald

JaredCasper

ChiCaoMinh BrianD.Carlstrom WoongkiBaek ChristosKozyrakisKunleOlukotun

ComputerSystemLaboratory StanfordUniversity http://tcc.stanford.edu

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SLIDE 2
  • TransactionalMemory
  • Problem:ParallelProgrammingishardandexpensive.

Correctnessvs.performance

  • Solution:TransactionalMemory

Programmerdefinedisolated,atomicregions Easytoprogram,comparableperformancetofinegrainedlocking Doneinsoftware(STM),hardware(HTM),orboth(Hybrid)

  • ConflictDetection

Optimistic:Detectconflictsattransactionboundaries Pessimistic:Detectconflictsduringexecution

  • Versionmanagement

Lazy:Speculativewriteskeptincacheuntilendoftransaction Eager:Speculativelywrite“inplace”,rollbackonabort

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SLIDE 3
  • !

Sowhat’stheproblem?(Haven’twefiguredthisoutalready?)

  • CoresarethenewGHz

Trendis2xcores/2years:2in‘05,4in‘07,>16notfaraway Sun:N2has8coreswith8threads=64threads

  • Ittakesalottoadoptanewprogrammingmodel

Mustlasttensofyearswithoutmuchtweaking TransactionalMemorymust(eventually)scaleto100sofprocessors

  • TMstudiessofaruseasmallnumberofcores!

Assumebroadcastsnoopingprotocol

  • Ifitdoesnotscale,itdoesnotmatter
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SLIDE 4
  • "

Lazyoptimisticvs.Eagerpessimistic

  • Lazyoptimistic
  • Optimisticparallelism
  • Fastaborts

Lazyoptimistic

  • Slowercommits… good

enough??

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SLIDE 5
  • #
  • Serialcommit⇒ Parallelcommit

At256proc,if5%oftheworkisserial,maximumspeedupis18.6x Twophasecommitusingdirectories

  • Writethrough⇒ writeback

Bandwidthrequirementsmustscalenicely Again,usingdirectories

  • Restoftalk:

AugmentingTCCwithdirectories Doesitwork?

Whatarewegoingtodoaboutit?

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SLIDE 6
  • $

ProtocolOverview

  • Duringthetransaction

Trackreadandwritesetsinthecache Tracksharersofalineinthedirectory

  • Twophasecommit

Validation:Markalllinesinwritesetindirectories

  • Lockslinefrombeingwrittenbyanothertransaction

Commit: Invalidateallsharersofmarkedlines

  • Dirtylinesbecome“owned” indirectory
  • Requireglobalorderingoftransactions

UseaGlobalTransactionID(TID)Vendor

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SLIDE 7
  • DirectoryStructure

0x1000 ….. 0x0004 0x0000 Owned Marked PN … P1 P0 Address SharersList

Directory

NowServingTID(NSTID) SkipVector

  • Directorytrackssharersofeachlineathomenode

Markedbitisusedintheprotocol

  • NowservingTID:transactioncurrentlybeingservicedbydirectory

Usedtoensureaglobalorderingoftransactions SkipvectorusedtohelpmanageNSTID(seepaper)

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SLIDE 8
  • %

CacheStructure

Data Tag SM SR Valid Dirty

Cache

SharingVector WritingVector

  • Eachcachelinetracksifitwasspeculativelyread(SR)ormodified(SM)

Meaningthatlinewasreadorwritteninthecurrenttransaction

  • SharingandWritingvectorsrememberdirectoriesreadfromorwrittento

Simplebitvector

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SLIDE 9
  • &

Commitprocedure

  • Validation

RequestTID Informalldirectoriesnotinwritingvectorwewillnotbewritingtothem(Skip) RequestNSTIDofalldirectoriesinwritingvector

  • WaituntilallNSTIDs≥ ourTID

Markalllinesthatwehavemodified

  • CanhappeninparalleltogettingNSTIDs

RequestNSTIDofalldirectoriesinsharingvector

  • WaituntilallNSTIDs≥ ourTID
  • Commit

Informalldirectoriesinwritingvectorofcommit Directoryinvalidatesallothercopiesofwrittenline,andmarkslineowned

  • Invalidationmayviolateothertransaction
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SLIDE 10
  • ParallelCommitExample

NSTID:1Directory0 P1P2MO X … NSTID:1Directory1 P1P2MO Y … TID Vendor Tid:? P2 Tid:? P1

Load X DataX DataY LoadY LDY STY Commit LDX STX Commit

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SLIDE 11
  • P2

P1

ParallelCommitExample

NSTID:1Directory0 P1P2MO X … NSTID:1Directory1 P1P2MO Y … TID Vendor

LDY STY Commit LDX STX Commit TIDReq. TID=1 TIDReq. TID=2

Tid:2 Tid:1 Tid:? Tid:?

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SLIDE 12
  • NSTID:1

ParallelCommitExample

Directory0 P1P2MO X … Directory1 P1P2MO Y … TID Vendor Tid:2 P2 Tid:1 P1

NSTIDProbe NSTIDProbe LDY STY Commit LDX STX Commit

NSTID:2 NSTID:1

Skip1

Skip2

NSTID:1 NSTID:2

NSTID:3

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SLIDE 13
  • !

ParallelCommitExample

NSTID: 2Directory0 P1P2MO X … NSTID:1Directory1 P1P2MO Y … TID Vendor Tid:2 P2 Tid:1 P1

MarkX MarkY LDY STY Commit LDX STX Commit

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SLIDE 14
  • "

ParallelCommitExample

NSTID: 2Directory0 P1P2MO X … NSTID:1Directory1 P1P2MO Y … TID Vendor Tid:2 P2 Tid:1 P1

Commit Commit LDY STY Commit LDX STX Commit

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SLIDE 15
  • #

ConflictResolutionExample

NSTID:1Directory0 P1P2MO X … NSTID:1Directory1 P1P2MO Y … TID Vendor Tid:? P2 Tid:? P1

Load X DataX DataY LoadY LDY LDX STX Commit LDX STX Commit

…

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SLIDE 16
  • $

ConflictResolution Example

NSTID:1Directory0 P1P2MO X … NSTID:1Directory1 P1P2MO Y … TID Vendor Tid:? P2 Tid:?

DataX LoadX TIDReq. TID=1

P1

LDY LDX STX Commit LDX STX Commit

… Tid:1

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SLIDE 17
  • ConflictResolution Example

NSTID:1Directory0 P1P2MO X … Directory1 P1P2MO Y … TID Vendor Tid:x Tid:1 P1

NSTIDProbe NSTIDProbe TIDReq. TID=2 Skip1

P2 Tid:2 NSTID:1 NSTID:2

LDX STX Commit

…

LDY LDX STX Commit

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SLIDE 18
  • %

ConflictResolution Example

NSTID:1Directory0 P1P2MO X … Directory1 P1P2MO Y … TID Vendor Tid:2 P2 Tid:1 P1

NSTID:1 Mark:X NSTIDProbe NSTID:3 Skip2 NSTID:1

NSTID:2 NSTID:3

LDX STX Commit

…

LDY LDX STX Commit

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SLIDE 19
  • &

ConflictResolution Example

Directory0 P1P2MO X … NSTID:3Directory1 P1P2MO Y … TID Vendor Tid:2 P2 Tid:1 P1

Commit InvalidateX

Violation!

LDX STX Commit

…

LDY LDX STX Commit

NSTID:1 NSTID:2

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SLIDE 20
  • ConflictResolution Example(Writeback)

NSTID:2Directory0 P1P2MO X … NSTID:3Directory1 P1P2MO Y … TID Vendor Tid:2 P2 Tid:1 P1

Request:X WB:X DataX LoadX LDX STX Commit

…

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SLIDE 21
  • Evaluationenvironment

1pernode,10cyclelatency Directory 100cyclelatency MainMemory 2Dgridtopology,14cyclelinklatency Interconnection 512KB,32bytecacheline,8way,16cyclelatency L2 32KB,32bytecacheline,4way,1cyclelatency L1 1 64singleissuePowerPCcores CPU

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SLIDE 22
  • ItScales!
  • "

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barnes radix SVMClassify equake

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SLIDE 23
  • !

Resultsforsmalltransactions

volrend water nsquared

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  • "

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SLIDE 24
  • "

LatencyTolerance

  • !

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  • "

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  • "

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  • "

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  • /0+
  • 1(
  • 2

swim radix waterspatial $%&"

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SLIDE 25
  • #

Remotetrafficbandwidth

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3 3# 3 3 # 3 3# 3!

  • +

4 5+ (* 6 7( 6 8+ ( 9

  • :7(
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SLIDE 26
  • $

Takehome

  • TransactionalMemorysystemsmustscaleforTMtobeuseful
  • LazyoptimisticTMsystemshaveinherentbenefits

Nonblocking Fastabort

  • LazyoptimisticTMsystemscale

Fastparallelcommit Bandwidthefficiencythroughwritebackcommit

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SLIDE 27
  • Questions?

Whew! JaredCasper

jaredc@stanford.edu

ComputerSystemsLab StanfordUniversity http://tcc.stanford.edu