A low-latency, high-performance versatile SerDes I nterface I P - - PowerPoint PPT Presentation

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A low-latency, high-performance versatile SerDes I nterface I P - - PowerPoint PPT Presentation

Mar 25, 2024 103 likes •261 views

A low-latency, high-performance versatile SerDes I nterface I P Dr. Mondrian Nssle IP-SOC2017, December 2017, Grenoble mondrian.nuessle@extoll.de EXTOLL Background German high-performance computing hardware (networking) and IP

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SLIDE 1

A low-latency, high-performance versatile SerDes I nterface I P

  • Dr. Mondrian Nüssle

IP-SOC2017, December 2017, Grenoble

  • mondrian.nuessle@extoll.de
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SLIDE 2

EXTOLL Background

  • German high-performance computing

hardware (networking) and IP design company

  • Spin-off from U. of Heidelberg
  • Based in Mannheim
  • EXTOLL started with HPC network designs

+ Added IP & Design Services

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 3

Low-latency interconnects

  • Low-latency networking

and interconnects important

  • Parallel computing (MPI,…)
  • Other applications as well!
  • EXTOLL Tourmalet is the

lowest-latency HPC interconnect (network) solution today

  • 0.810µs application-to-

application MPI latency

  • (Ethernet, typical: 5-10µs…)

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 4

EXTOLL ASIC – Tourmalet

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  • ASIC specifically designed for HPC
  • x16 PCIe gen3 connectivity
  • High sustained message rate

(> 80M messages/s)

  • Low latency message exchange (~ 0.8us)
  • 7 Links, 12 lanes of up to 100Gb/s per

direction and link

  • 8.9GB/s MPI bandwidth
  • 640 MHz Clock frequency
  • 270M transistors
  • ~ 60ns Hop latency
  • > 100 SerDes instances!

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 5

SerDes

  • SerDes IP is one of the fundamental building blocks of

todays high-speed networking

  • EXTOLL found available IP offerings not always optimal:
  • High data rates often only on latest nodes
  • Not cost efficient!
  • Not optimized for low latency applications
  • …
  • Design of in-house SerDes technology

A low-latency, high-performance versatile SerDes Interface IP

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D0 Serialization Deserialization Serial Data Parallel Data D0...D7 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Parallel Data

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SLIDE 6

High-Speed Links

A low-latency, high-performance versatile SerDes Interface IP

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Transmission Channel Serializer Deserializer

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SLIDE 7

High-Speed Links

A low-latency, high-performance versatile SerDes Interface IP

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Transmission Channel Serializer Deserializer

  • Equalization

(TX & RX)

  • CDR
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SLIDE 8

Digital-centric design

  • High speed SerDes architecture

based mainly on digital logic

  • Complemented by advanced

verification and modelling methodology

  • Minimum number of analogue and

full custom components

  • Keep complexity in synthesizable

RTL code

  • Enforce consistency between model

and implementation

  • Various digital control and tuning

loops for robust performance

  • Flexible, robust architecture; easy to

migrate to other technologies; adaptation to customer applications

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 9

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Important Features

  • SerDes PHY is combined from transceiver lanes and clock generation block
  • Flexible number of transceivers in one block
  • Common high speed PLL for line rates @ 2.5 to 28 Gbps
  • Programmable transmitter with equalizer (4 tap FIR)
  • Programmable linear RX equalizer (CTLE)
  • Programmable discrete RX equalizer (5 tap DFE)
  • Digital Clock Data Recovery (CDR)
  • Comprehensive suite of calibration circuits/loops
  • Support for PCIe specific features

(Far end RX detect, Electrical Idle,..)

  • Diagnostic features:
  • Pattern generators
  • Concurrent Eye Monitor for equalization and

channel analysis

  • Far End and Near Loopbacks
  • Analog testbus
  • Available for 28nm/22nm processes!

A low-latency, high-performance versatile SerDes Interface IP

RX macro TX macro Digital Logic

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SLIDE 10

Block Diagram

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 11

Low-Latency!

Examples of low-latency optimizations:

  • TX Side
  • No sync FIFOS needed for multi-lane

implementations

  • No additional stage for FIR equalizer
  • RX Side
  • no time lost in 5-tap DFE due to quarter rate

architecture

  • 0-stage bitslip logic for word alignment instead of

1-2 stage barrel shifter logic

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 12

Design state & Silicon

  • 8-lane test chip
  • Tape-out in TSMC 28nm HPC+

in summer 2017

  • Package and test board design
  • Done!

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 13

Summary

  • Unique low-latency features
  • Support for latest PCIe, Ethernet,

et al. Rates (16Gbps, 25.x, 28.x,…)

  • High data rates (more than

12.5Gbps!) available for planar

28/ 22nm processes

(cost efficient nodes)

  • Silicon proven

(TSMC 28nm HPC+ )

  • Cost efficient licensing

A low-latency, high-performance versatile SerDes Interface IP

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SLIDE 14

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Thank You! Contact us:

info@extoll.de

Come and see us at the exhibition!

A low-latency, high-performance versatile SerDes Interface IP