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3D Integrated Technology at Fermilab Activities and Plans - - PowerPoint PPT Presentation

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3D Integrated Technology at Fermilab Activities and Plans MarcelDemarteau FortheFermilabDetector&PhysicsR&DGroup 3DIntegratedTechnologiesPerspectives FirstworkshoponLHC$ILCprospects

slide-1
SLIDE 1

3D Integrated Technology at Fermilab

Activities and Plans

MarcelDemarteau

FortheFermilabDetector&PhysicsR&DGroup

3DIntegratedTechnologiesPerspectives FirstworkshoponLHC$ILCprospects

November29$30,2007

slide-2
SLIDE 2

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 2

Fermilab

  • LocatedinthewesternsuburbsofChicago,Illinois,on2750hectaressite
  • 1950employees;2500usersofwhom1000fromabroad
  • Currentlyhighestenergymachineintheworld:theTevatron
  • Currentlyhighestintensityneutrinobeamintheworld
  • Aworldclassastrophysicsprogram
  • Fermilab

Fermilab’ ’s s ScientificProgram ScientificProgram

  • EnergyFrontier
  • NeutrinoFrontier
  • ParticleAstrophysics
  • TheonlyUSlab.solely

devotedtoparticle physics

slide-3
SLIDE 3

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 3

Fermilab Organization

  • MostofthedetectorR&DcarriedoutintheParticlePhysicsDivision
  • ~150physicistsassociatedwithexperiments
  • 84employeesinMechanicalDepartment
  • 54employeesinElectricalDepartment
  • R&Dsupportedbyuserfacilities
  • SiliconDetectorFacility

!" "#

  • TestBeamArea

$%

&' () &' () *' +,()

Testbeam Silicon Facility

slide-4
SLIDE 4

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 4

Past Projects

  • ASICDesignsforsiliconstripandpixeldetectors,digitalcalorimetry,trigger

pipeline,voltagecontrolandgenerationandmonitoring

  • CDS,analogpipelines,WilkinsonADCs,datasparsification
  • SiliconStripandPixelDetectors

SVX4 DCAL Trip-T FPIX-2 FRIC0 RMMC

slide-5
SLIDE 5

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 5

Fermilab Perspective

  • Ourphilosophy:detectorR&Dthatisofhighenoughcaliberwill beapplied

inanyfutureexperiment

  • Focusonwhatwebelievearethemostpromisingtechnologies
  • Buildonoursignificantstrengthandstrongexpertiseinengineeringfor

siliconparticledetectors– bothelectricalandmechanical

  • AlldetectorR&Discarriedoutwithalongtimescaleinmindandwithin

abroadcontext:ILC,LHCupgradeandapplicationsbeyond

  • Adoptafullyintegratedapproach:sensordevelopment,associated

readout,powerdelivery,mechanicalsupport,beamtests

  • Fermilab effort in 3D Integrated Technology
  • Contextofourinitialeffort:ILCchallenge
  • 3DandSOI

SOITechnology 3DTechnology

  • ThinnedsensorR&D
  • LaserAnnealing
  • Powerdistribution
  • MechanicalSupport
slide-6
SLIDE 6

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 6

ILC Pixel Detector

  • Pixeldetectorrequirements
  • Verylowmass:0.1%X0 perlayer

(equivalentof100µ µ µ µmofSi)

  • Lowpowerconsumption(~50Wfor

1Gigapixels)

  • Highresolutionthussmallpixelsize
  • ModestradiationtoleranceforILCapplications
  • Combinationofsmallpixels,shortintegrationtime,

lowpowerrequiredforILCisdifficulttoachieve

  • Smallpixelstendtolimittheamountof

circuitrythatcanbeintegratedinapixel

  • Smallpixelsalsomeanthatthepower/pixel

mustbekeptlow

  • Thelowoccupancy/pixel/train(~0.5%)meansthat

asparsescanarchitecturewouldbeappealingif:

  • Signal/noiseishigh
  • Enoughelectronicscanbeintegratedonapixel
  • Wefeelthatthebestprospectsforanoptimalvertexdetectorarethe

verticalintegration(3D)andrelatedSOItechnologies.Theseofferthe prospectofthin,denselyintegrated,deviceswithexcellentsignal/noiseand lowpower.3Dalsooffersprospectsforintegrationofpowermanagement intothepixelstructure. 969 µs 969 µs ~199 ms

ILCBeamstructure: Fivetrainsof2625bunches/sec Bunchseparationof369.2ns

slide-7
SLIDE 7

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 7

SOI Detector Concept

  • BondedWafer:lowresistivetoplayer+highresistivesubstrate,separated

throughaBuriedOXide (BOX)layer

  • Toplayer:standardCMOSElectronics(NMOS,PMOS,etc.canbeused)
  • Bottomsubstratelayerformsdetectorvolume
  • ThediodeimplantsareformedbeneaththeBOXandconnectedbyvias
  • Monolithicdetector,nobumpbonds(lowercost,thindevice)
  • Highdensityandsmallerpixelsizeispossible
  • Smallcapacitanceofthesensenode(highgainV=Q/C)
  • Industrialstandardtechnology(costbenefitandscalability)

Advantages

  • 100%fillfactor
  • Largeandfastsignal
  • Smallactivevolume:high

softerrorimmunity

  • FulldiHelectricisolation:

latchup free

  • LowJunctionCapacitance:

highspeed,lowpower

SOI Pixel Detector

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SLIDE 8

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 8

SOI Detector Development

  • SOIdetectordevelopmentisbeingpursuedbyFermilabatthreedifferent

foundries:

  • MITHLincolnLaboratorythroughMultiHProjectWafersubmission(DARPAfunded)
  • OKIElectricIndustryCo.Ltd.inJapanthroughMultiHProjectWafersubmission(KEK)
  • AmericanSemiconductorInc.(ASI)inUS,throughSBIRphaseIgrant(Cypress

semiconductor)

Conceptualdesign Simulation TestStruct. 3Dchip TestStruct. MamboI Laseranneal Work underway TestStructures Sensors MITHLL:3DRunII 3DDedicated OKI:Mambo II Work planned 200nm 400nm 200nm BuriedOxide Partiallydepleted dualgate Fully depleted Fully depleted Transistor type 200mm 150mm 150mm WaferØ 180 180 150 150 200 Featuresize (nm) ASI MITHLL OKI

slide-9
SLIDE 9

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 9

Pixel Design in OKI Process

  • MAMBOChip:MonolithicActivepixelMatrixwithBinarycOunters
  • Awidedynamicrangecountingpixeldetectorplusreadoutcircuitry,sensitiveto

100H400keV electrons,highenergyXHrays,andminimumionizingparticles, designedintheOKI0.15micronprocess

  • OKIprocessincorporatesdiodeformationbyimplantationthrough theBOX
  • Chiparchitecture(simplifiedduetodesigntimeconstraint):

amplifier– shaper– discriminator– binarycounter

  • DesignsubmittedDec.15,’06
  • ChipdeliveredJune’07
  • Characterizationofteststructures

underway

  • Arraysize64x64pixels,26µ

µ µ µmx26µ µ µ µm

  • 13Nmimplantpitch,tominimizethe

“backgate” effect

  • &&-
  • 350microndetectorthickness

13um

26 µm

see talk by Ray Yarema

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SLIDE 10

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 10

Pixel Design in ASI Process

  • SBIRPhaseIgrantwithAmericanSemiconductor(ASI),Boise,Idaho
  • ASIprocess(0.18µ

µ µ µm)basedonanSOIdualgatetransistorcalledaFlexfet™ – Flexfet hasatopandbottomgate

  • Bottomgateshieldsthetransistor

channelfrom # ""&#./0" % )#" #" 1# 21&

  • Modelingandprocesssimulation
  • fathinned,fullydepleted

sensor/readoutdevice.

  • CircuitdesignforILCpixelcell

)&2 3&- &4 &4 1## "&"## &

http://www.americansemi.com/

DiodesimulationinFlexfetprocess

see talk by Ray Yarema

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SLIDE 11

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 11

MIT-Lincoln Laboratory 3D Process

  • MITLincolnLaboratories(MITHLL)isafederallyfunded(Airforce)research

anddevelopmentcenterofMIT

  • Ithasdevelopedthetechnologythat

enables3Dintegration

  • Demonstratedthe3Dtechnology

throughfabricationofimagingdevices

  • ItoffersaDARPAfunded

3DMultiHProjectWaferRun

  • WeparticipatedinthelastMITHLL

threeHtiermultiHprojectrun

  • 3DdesigntobelaidoutinMITHLL

0.18µ µ µ µmSOIprocess

  • /&11'

./05"515 #64&6&

  • 3levelsofmetalineachlayer
  • VIPchipdesignsubmittedOct.15,2006
  • Pixelsize20x20µ

µ µ µm;64x64pixelarray

  • Nointegratedsensor

Tier3 8.26m Tier2 7.86m Tier1 6.06m

  • xideHoxidebond

3DVia

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SLIDE 12

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 12

  • Firstdesignwhich,in

principlemeets‘all’ of theILCrequirements forthickness,resolution, powerdissipation,time stamping

  • Poweris0.75

microwatt/pixel ~18.75 microwatts/mm2 (afterpulsing)

  • Noiseis~30H40eH
  • S/N=100H200:1

Pixel Design in MIT-LL Process

  • Design:
  • Analogueandbinaryreadoutinformation
  • TimestampingofpixelhitforILCenvironment
  • 71 "#+8, 9
  • Sparsification toreducedatarate
  • :2&#6#24#""&"

7""5## &"&6 %66#-4 %46"

  • Chipdividedinto3tiers
  • 7-% "%"%-%
  • ChipreceivedNov.20,2007;beingtested

Integrator Discriminator Analog out Time stamp circuit Test inject Read all R S Q Pixel skip logic Write data D FF Data clk Read data To x, y address T.S.

  • ut

Hit latch Vth Analog front end Pixel sparsification circuitry Time stamp

Schematicpixelcell blockdiagram see talk by Ray Yarema

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SLIDE 13

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 13

Modeling 3D Circuits

  • AppliedforanSBIRPhaseIgrantwithCFDResearchCorporation

(www.cfdrc.com)todevelopautomateddesigntoolsfordetectorand electronicsintegrationwhichwillallowtheextractionofphysical parametersofthesedevicesbasedontheintegratedcircuitlayout

  • Modelingandanalysisofradiationeffects
  • Modelingofthermalandmechanicalproperties

Tier 2 Tier 3 Tier 1 675 um

Si Substrate

M3 M3 M2 M2 M1 M1 BM1 M3 M2 M1

MIT-LL 3D Layer Description CFDRC Full 3D Model

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SLIDE 14

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 14

Towards Integrated Detectors

  • IntheSOIprocess,thehandlewafercan

behighquality,detectorgradesilicon: integrationofelectronicsandfully depleteddetectorsinasinglewaferwith veryfinepitch– ourultimategoal

  • Inourapplicationsthedetectorlayeris

atmost50µ µ µ µmthick

  • SensorIssues:
  • SOIprocesseswhichincludeprocessingofthehandlewaferaspartof

thefabricationprocessoftenneedthinningofthebackside

  • Afterthinningabacksidecontactmustbeformed.
  • ThecurrentMITHLLMPWrundidnotprovideuswithadetectortier
  • SensorR&D
  • Laserannealing
  • Developmentofedgelesssensors
  • Devicebonding
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SLIDE 15

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 15

Laser Annealing

  • Problem:AfterthinningprovideabacksideOhmic contactwhilekeepingthe

topsidebelow~500degCtoprotecttopsideCMOSSOIcircuitry

  • Usuallydonebyimplantationandhightemperaturefurnaceannealing
  • We,incollaborationwithCornellUniversity,aredevelopingalaser

annealingcapabilityofbacksideimplantation:

  • UsearasterscannedExcimer Lasertomeltthesiliconlocally

;#1#/# &&#& % %< #

  • Studyandqualificationofprocess
  • 300µ

µ µ µmthicksiliconstripdetectors (Hamamatsu),4x10cm2 withlow leakagecurrent

  • Backgrind by~50micronstoremove

backimplantandaluminization

  • Polish,reHimplantdetectorusing10KeV

phosphorusat0.5and1.0x1015/cm3

  • LaserannealandmeasureCVandIVcharacteristics

=.>4 55?5 4 ? +,

  • P

r e l i m i n a r y

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SLIDE 16

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 16

  • Diodeimplants

2

  • µ

m

  • 3Dchipprovidesonlyreadout.Inparallelwehavedesignedmatingsensors
  • n6”,highresistivity,floatHzone,nHtypewaferstobebondedto3Dchips
  • SensorfabricationperformedatMITHLL
  • Thinnedto50,75,100microns
  • Sensorssensitivetotheedge,

4Hsideabuttable,i.e.nodeadspace

  • Deeptrenchetch,ndopedpolyHsilicon

fillprovidesedgedoping

  • R&DProgram
  • Validateanddevelopthinningprocess

withlaserannealing

  • Validatethetechnologywhichprovides

thinneddetectorssensitivetotheedge

  • Measuretheactualdeadregioninatestbeam
  • Studyradiationeffects(SLHC)
  • Understandperformance
  • BondwithVIPreadoutchip
  • Useinconstructionofmechanicalprototypedetectors

Development of Thinned Edgeless Sensors

Implantwith laserannealing Trenchon detector edgefilled withpoly andconnected tobottom implant Detector bias Toother pixels

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SLIDE 17

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 17

  • MasksdesignedatFNAL
  • Teststructures
  • Stripdetectors

,

  • FPiX2pixeldetectors

,-µ&- ." .

  • Detectorstomateto3Dchip
  • µ&-
  • WafersreceivedatFermilabNov.2007
  • Growingpainsremovinghandlewafer
  • VImeasurementsbeingcarriedout
  • Nextstepistobondsensortoreadoutchip

Development of Thinned Edgeless Sensors

Strip detectors Fpix2 pixel detectors Strip detectors 3D test detectors Test structures MIT-LL Wafer designed at FNAL

  • 20µ

µ µ µm

3DChipsensor

n++ n+

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SLIDE 18

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 18

Device Bonding

  • Sensorproductionprovides
  • 50x400µ

µ µ µm2 pixelarrays

  • 20x20µ

µ µ µm2 pixelarrays

  • Needtobondsensorwithreadout

chip

  • 50x400µ

µ µ µm2 ➠ ➠ ➠ ➠ FPIX2chip

  • 20x20µ

µ µ µm2 ➠ ➠ ➠ ➠ VIP3Dchip

  • Pursuingtwotechnologies:

CuHSn (RTI)andDBI(Ziptronix) Bonding Techniques

  • Ziptronix:DirectBondInterface
  • Techniqueuses“magicmetal” plus
  • xidebond
  • >"6
  • ="#&#"

6

  • ;##&,µ

"6µ

  • &
  • 7 &
  • RTI:CuHSn Bondprocedure
  • TechniqueusesCupillarswith

diameterlimitedto7µ µ µ µm

  • ;&&

6"@>- &

  • .@>0A/&-%

""4 #"

slide-19
SLIDE 19

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 19

Mechanical Design and Serial Power

  • DevelopingtechniquesforfabricatingandhandlingthinHwalledcarbonfiberstructures
  • MultiHlayered,highprecision,verythin,lowmassdetectors
  • ILCgoal:layerthicknessof0.1%X0 perlayer,

equivalentof100µ µ µ µmofSi

  • LHCgoal:lowestmaterialbudgetaspossible
  • PrototypesofcarbonHfibersupportstructures
  • FabricationofprototypehalfHshellstructures

forevaluationandtesting

  • ComparisonwithFEAanalyses
  • Peakandaveragepowerarecrucialissuesforthenext

generationofparticledetectors

  • Serialpoweringcanlowerinstantaneouscurrent
  • Fermilabisdesigningaserialpoweringchipincollaboration

withPenn/RAL

  • Designofashuntregulatorbeingcapableofregulating

upto1A@2.5V

  • Twolinearregulators(analoganddigital)switchable

betweentwodownloadablevoltages

  • Corevoltageforchipcontrol(1.5to2.5V)
  • TSMC0.25micron(radiationtolerantdesign)
  • Concerns:
  • Currentbalanceandtorques

Prototype

slide-20
SLIDE 20

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 20

Summary of Current Projects

  • SOI
  • OKIMultiProjectWaferrun;testofMambochip
  • OKIteststructureirradiation
  • MITHLLteststructures
  • ASIsensordesignwithdualgatetransistor
  • 3D
  • StudiesofdevicesthinnedatIZM
  • VIP1chiptests
  • BondingStudies

"4 6#A; 7.6#B&-

  • Sensors
  • Hamamatsusensorthinningandlaserannealstudies
  • OKIwaferthinningandlaserannealstudies
  • MITHLLsensortesting
  • PowerandMechanics
  • Serialpowerchip(Fermilab,Penn,RAL)
  • Fabricationandtestingofthincarbonfibersupportstructures
  • TestBeam
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SLIDE 21

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 21

Future Projects

  • SOI
  • OKIhas2nd MPWrun,200nmSOIprocess;submitMamboIIchip
  • ThroughPhaseIISBIRgrant,obtainsensorsfromASI
  • 3D
  • ExpectthirdMITHLLDarpa 3DMPWrun;submitVIPHIIchip
  • 3DsimulationstudieswithCFDRC
  • Consideringdedicated2HTier3Drun,withlayoutononewafer

$-&5 5"#&

A B B A A B B A Top Wafer Bottom Wafer A B B A Flip Horz. Note: top and bottom wafers are identical. Typical frame

  • Sensors
  • ContinuedR&Donthinnedsensors
  • PowerandMechanics
  • Submissionofserialpoweringchip
  • Developmentofthincarbonfiber

supportstructures

  • TestBeam
  • Expecttohavebeamtestofall

components

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SLIDE 22

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 22

Far Future

  • Forwardpixeldetectorsarenotoriouslydifficulttobuildinlowmass,low

powerconfigurationwithverylittleadditionalmassduetocables

  • Maybe,oneday,afull3Dwafer

willbedevelopedthatcontains allthefunctionalityneededfor atrackingpixeldetector

  • Shaper,amplifier,DCS
  • ADC,pipeline
  • Hitaddressing
  • Timestamping
  • Sparsification
  • Continuousreadout
  • Deadtime lessoperation
  • Lowpower
  • …
  • …

R=6cm

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SLIDE 23

3D IT Workshop, Nov. 29-30 -- M. Demarteau Slide 23

Summary

  • Weseethedevelopmentofthe3Dtechnologyasholdingalotofpromisefor

thedevelopmentofparticlephysicsdetectors

  • VeryactiveR&DprogramatFermilabonthedevelopmentof3Dtechnology

coveringallaspectsofitsdesignasparticlevertexdetector:

  • Readoutandsensordevelopment
  • Devicecharacterization
  • Powerandmechanicalsupport
  • Beamtests
  • TheR&Dprogrambuildsontheexistingstrengthsatthelaboratory
  • ThisworkhasaninitialfocusontheILCbutweviewitinasbroadacontext

aspossiblewithinthelaboratoryincludingLHC,synchrotronradiationxHray detectorsaswellasmedicalapplications

  • AlldetectorR&Discarriedoutwithalongtimescaleinmindandweare

willingtopartnerwithcollaboratorsfromindustry,universitiesandother researchinstitutions