2012 EOS/ESD Symposium ESD Dynamic Methodology for Diagnosis and - - PowerPoint PPT Presentation

2012 EOS/ESD Symposium ESD Dynamic Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events

Ting-Sheng Ku, Jau-Wen Chen, George Kokai, Norman Chang, Shen Lin, Yu Liu, Ying-Shiun Li, Bo Hu

Outline

• Introduction
• ESD dynamic analysis methodology
• Requirements for ESD dynamic simulation
• Application Examples
• Summary

Slide 2

Worsening Trend in ESD

• Thinner oxide, lower junction

thermal breakdown voltages

• Reduced failure current

density limit

• Worsening CDM issue for

high-frequency designs

White paper 2: A case for lowering component level CDM ESD specifications and requirements, April, 2010

Slide 3

ESD Dynamic Analysis Methodology

• Perform diagnosis of potential failure mechanisms when

silicon failures occurred

• Verify fixed solution robustness by comparing differential

stressed values of the failed junctions

• Strategic check on potential CDM design weaknesses

before tape-out on mixed-signal / IO blocks

Slide 4

Target Applications for ESD Dynamic Analysis

• Initial target users are ESD experts
• Eventual usage by mixed-signal macros designers
• Transistor count per macro : ~200K in most cases and

can go up to ~1M

• What can a dynamic ESD check provide beyond a

static one?

• Physically correct modeling of CDM discharging behavior
• Explicit detection of worst transient voltage stressed junctions
• Evaluation of clamp transient effectiveness related to design

and placement

• Ability to perform trade-off on peak versus duration device

failure mode

Slide 5

Cross-domain Check and Possible CDM Failure Mechanism

for possible Vgs junction failure due to disparate discharging rate from gate and source nodes to CDM grounded pin. See more CDM checks in “ESD Electronic Design Automation Checks”, Technical report # TR 18.0-01-11

Power Clamp 1 Power Clamp 1

Rbus VDD2 VDD1 VSS1 VSS2 GND

• +

Vgs

Outline

• Introduction
• ESD dynamic analysis methodology
• Requirements for ESD dynamic simulation
• Application Examples
• HBM event
• CDM event
• Summary

Slide 7

Requirements for ESD Dynamic Simulation

• Modeling
• Handling of snap-back

behavior in clamp

• P/g RLC and coupled signal RC
• Substrate R/C and Well diodes
• Nonlinear devices modeling w/

high voltage consideration

• High performance and large capacity for the

post-layout macro designs

Metal Grid RLC and Substrate Model

• Metal grid L extraction needed in addition to RC for fast slew rate
• Extraction of substrate well diodes and RC grid
• Modeling of distributive effect due to substrate

Slide 9

P-well N-well P-substrate

Modeling of Capacitance between Chip Substrate to Charging Plate

Courtesy of J. Karp, EOS/ESD Sym 2008

Slide 10

• Cdut is defined as between the silicon die and metal lid that is

separated by Thermal Interface Material (TIM)

• This figure of merit can be used to tune the Ipeak of Pogo pin

to match user’s expected Ipeak in simulation

It was observed that the target CDM and HBM simulation block size can be reduced from full-chip to a smaller circuit block containing the zapping

• pin. The requirements are

1. Primary ESD discharge paths must be included 2. Simulation coverage is limited to the simulated circuit block only 3. The Pogo pin peak current can be maintained through tuning of substrate_to_gnd_cap to satisfy JEDEC standard Following these steps ensure consistent absolute stress value. More importantly little impact on failure junction ranking

The Impact of Simulated Block Size on the Stress Ranking and Value

Slide 11

Smaller circuit block Bigger circuit block

Block-based ESD Dynamic Flow

Slide 12

• Import DSPF (Detailed Standard Parasitic Format) of coupled signal

RC netlist and create P/G contact pins

• Extract metal grid RLC, substrate RC, and well diodes
• Hook up the two netlist above through contact pins and create test

bench for HBM or CDM zapping condition

• Perform the simulation on the final netlist above and generate

junction stress report

Outline

• Introduction
• ESD dynamic analysis methodology
• Requirements for ESD dynamic simulation
• Application Examples
• HBM event
• CDM event
• Summary

Slide 13

sig

_

AGND AVDD

sig

_

AGND AVDD

Pwell guard ring grounded Pwell guard ring floating

• Both test cases with AGND -2000V HBM zap and AVDD

grounded

• Case with P-well guard ring grounded failed HBM test,

while case with P-well guard ring floating passed

Failed clamp Passed clamp

HBM Case Comparison : Failed/Passed Test due to Grounded vs. Floating P-well Guard Ring in RC-based Clamp

Slide 14

Snapshot of HBM Failure Case

Lab de-processed result of failed HBM test

• n I/O with P-well guard ring grounded

Slide 15

sig

_

AGND AVDD

P-well guard ring grounded

Failed clamp

HBM Test Case

• Device count :

12K subckt (xmos), 6K Diodes

• Extracted elements:

5.79M RLCs

• Simulation Conditions: Initialized at -2000V (HBM test)

HBM Analysis setup – 48min simulation : 16hr Peak memory – 15 GB P/G RLC Substrate RC w/ Well diode

Macro Block w/ coupled signal RC

3.0u

1525ohm

100pf GND VDD

AGND

Zap

0.1f

AVDD Init at -2000V

Slide 16

HBM Failure on Melt-down of Center Finger of RC-based Clamp Due to Parasitic BJT Turn-on

• Center finger furthest from Pwell grounded guard ring resulting in largest

resistance from the AGND zap point

• Vbs of finger higher due to substrate node distance from Pwell guard ring
• Higher Vbs of center finger with higher Ids current may turn on parasitic

bipolar earlier than other fingers, causing center finger melt down

AGND AVDD X Center Finger of RC-based Clamp

Slide 17

D/G/S/B Node Waveforms of the RC-based Clamp Fingers with Substrate Pwell Guard Ring Grounded

Vg

Vb of different fingers w/ the center finger having largest Vbs

Vs Vd

1.37ns

Vbs of different clamp fingers are very different in amplitude, with center finger having largest Vbs making non-uniform turn-on

• f the center finger, and triggering its parasitic BJT

Slide 18

D/G/S/B Node Waveforms of the RC-based Clamp Fingers with Substrate Pwell Guard Ring Floating

Vg Vb of different fingers Vs Vd

1.37ns

Vbs of different clamp fingers are similar in amplitude, making the uniform turn-on among all fingers

Slide 19

Worst Stress Movie for HBM AGND -2000V Zap with Hot Spot on Center Finger of RC-based Clamp

Hot spot at 1.37nsec of the HBM zap at the center RC-based clamp finger

Slide 20

Outline

• Introduction
• ESD dynamic analysis methodology
• Requirements for ESD dynamic simulation
• Application Examples
• HBM event
• CDM event
• Summary

Slide 21

Example CDM Test Case

• Device count :

62,256 subckt (xmos), 541 Diodes

• Extracted elements: 3,709,648 RLCs
• Simulation Conditions: Initialized at -500V (CDM test)

P/G RLC Substrate RC w/ well diode

Macro Block w/ coupled signal RC

Lpogo Rpogo Cpogo

GND VDD VDDP

IOP ION

Zap

Cdut of 3pF evenly distributed among substrate and can be tuned to match expected pogo pin peak current CDM Analysis setup - 1hr20m simulation : 8hr25m Peak memory – 25 GB

Slide 22

Example CDM Failure due to Race Condition in Discharging Paths

• Impedance mismatch between I/O (sig) and LDO bias net caused

large Vgd junction stress on -500V zap due to bias net being heavily referenced to ground

Worst Junction Pogo pin current waveform Worst junction voltage waveform

Slide 23

Stress Movie on the CDM Test Case : IOP Zap at -500V

• 500V Zap at IO Pin

Highest stress occurred at failed junction (Vgd) on the top around 137psec; the 2nd ranked stressed junction with the similar design issue except the IO transistor size is much larger

Slide 24

Failure Emission Image for the CDM Test Case

emission site

Lab emission result of failed CDM test on high-speed I/O

Slide 25

Addition of PMOS Passgate as Proposed Fix for Failed Junction Stress Reduction

• PMOS passgate inserted at gate of failed NMOS serves to

isolate junction from loading the bias net, which allows junction voltage delta to stay within device tolerance

Worst junction voltage waveform PMOS passgate inserted

Slide 26

Summary

• With tighter design margin in 65/45/28/20nm

technology nodes, ESD verification is a must for SoC, mixed-signal design, and custom designs

• A comprehensive ESD dynamic methodology
• utlined for diagnosis and predictive simulation
• f HBM/CDM discharging events
• Example test cases with failure point correlation

between simulation and silicon measurement provided

Slide 27