1 Background | Problems | Challenges | Design | Evaluation | Summary - PowerPoint PPT Presentation

SPEED 
 Resource-Ef+icient and High-Performance Deployment for Data Plane Programs Xiang Chen , Hongyan Liu, Qun Huang, Peiqiao Wang, Dong Zhang, 
 Haifeng Zhou, Chunming Wu

Control Plane Applications Monitor Security Routing Data Plane Programmable Switches (e.g., To+ino, Trident) 1 Background | Problems | Challenges | Design | Evaluation | Summary

Control Plane Applications Monitor Security Routing gen DP Programs (e.g., P4) Data Plane Programmable Switches (e.g., To+ino, Trident) 1 Background | Problems | Challenges | Design | Evaluation | Summary

Control Plane Applications Monitor Security Routing gen DP Programs (e.g., P4) input Program Deployment deploy Data Plane Programmable Switches (e.g., To+ino, Trident) 1 Background | Problems | Challenges | Design | Evaluation | Summary

Data Plane Program Deployment Input : data plane programs w/ match action tables (MATs) Pkt in MAC learn Switching Pkt out Routing ACL Program (4 MATs) 2

Data Plane Program Deployment Input : data plane programs w/ match action tables (MATs) Action Rules Pkt out Output hit Pkt in to Port1 MAC learn Switching details Match Pkt in Pkt.srcip Action else Pkt out Pkt.dstip Drop Routing ACL Program (4 MATs) Details of an MAT (ACL) 2

Data Plane Program Deployment Input : data plane programs w/ match action tables (MATs) Target : programmable switches w/ switch stages RAM for MAT rules ALUs for Actions of MATs Pkt in MAC learn Switching Pkt out Routing ACL S3 S1 S2 S4 Program (4 MATs) Switch Arch (4 stages) 2

Data Plane Program Deployment Input : data plane programs w/ match action tables (MATs) Target : programmable switches w/ switch stages Output : Mapping between an MAT and a stage Pkt in MAC learn Switching Pkt out Routing ACL S3 S1 S2 S4 Program (4 MATs) Switch Arch (4 stages) 2

Data Plane Program Deployment Input : data plane programs w/ match action tables (MATs) Target : programmable switches w/ switch stages Output : Mapping between an MAT and a stage Enable deployment of advanced network applications 
 (1) Software-de+ined measurement: FlowRadar, Martini, PINT, OmniMon, etc. (2) In-network acceleration: NetCache, NetChain, NetLock, Cheetah, etc. 
 (3) Traf+ic scheduling and optimization: PIFO, PIEO, HPCC, P4air, etc. 2 Background | Problems | Challenges | Design | Evaluation | Summary

Requirements of Program Deployment Given multiple input data plane programs: simultaneously deploy these programs on network 1. Resource ef+iciency given that switch resources are limited (e.g., <10 MB memory) 2. High end-to-end packet processing performance satisfy tight latency/throughput requirements issued by apps 3 Background | Problems | Challenges | Design | Evaluation | Summary

Limitations of Existing Solutions (1) Compiler design: RMT (NSDI’15), dRMT (SIGCOMM’17), etc. (2) Virtualization: Hyper4 (CoNEXT’16), P4Visor (CoNEXT’18), etc. 4 Background | Problems | Challenges | Design | Evaluation | Summary

Limitations of Existing Solutions (1) Compiler design: RMT (NSDI’15), dRMT (SIGCOMM’17), etc. (2) Virtualization: Hyper4 (CoNEXT’16), P4Visor (CoNEXT’18), etc. Support program deployment on a single programmable switch (1) Poor resource ef+iciency as scaling to multiple programs (2) Low performance due to lack of considering constraints (device connectivity, traf+ic routing, etc.) 4 Background | Problems | Challenges | Design | Evaluation | Summary

Goal Program#1 P#2 P#1 P#3 Program#2 Our Framework Input output ··· Programmable Networks Program#N Provide program deployment that achieves: (1) Resource Ef+iciency: make the best use of switch resources (2) High Performance: low latency and high throughput 5 Background | Problems | Challenges | Design | Evaluation | Summary

Challenges (1) Program diversity: case-by-case analysis and deployment 
 e.g., Count-Min (sequential layout), NetCache (branch-heavy) 6 Background | Problems | Challenges | Design | Evaluation | Summary

Challenges (1) Program diversity: case-by-case analysis and deployment 
 e.g., Count-Min (sequential layout), NetCache (branch-heavy) (2) Heterogeneous constraints: complicated problem solving 
 switch resource limitations vs. network-wide constraints (e.g., device connectivity) 6 Background | Problems | Challenges | Design | Evaluation | Summary

Challenges (1) Program diversity: case-by-case analysis and deployment 
 e.g., Count-Min (sequential layout), NetCache (branch-heavy) (2) Heterogeneous constraints: complicated problem solving 
 switch resource limitations vs. network-wide constraints (e.g., device connectivity) (3) Inter-device coordination: pkt scheduling among switches 
 to preserve original packet processing semantics 6 Background | Problems | Challenges | Design | Evaluation | Summary

SPEED Framework (1) Table dependency graph for program diversity (2) Program merging for achieving resource ef+iciency (3) One big switch for heterogeneous constraints (4) Inter-device packet scheduling for device coordination 7 Background | Problems | Challenges | Design | Evaluation | Summary

SPEED Framework (1) Table dependency graph for program diversity This Talk (2) Program merging for achieving resource ef+iciency (3) One big switch for heterogeneous constraints (4) Inter-device packet scheduling for device coordination 7 Background | Problems | Challenges | Design | Evaluation | Summary

Table Dependency Graph (TDG) Universal intermediate representation of data plane programs 
 T=(V T , E T ): a node in V T is an MAT; an edge in E T is an MAT dep L2/L3 routing program TDG for the program 8 Figures extracted from “Compiling Packet Programs to Recon+igurable Switches”, NSDI 2015

Table Dependency Graph (TDG) Universal intermediate representation of data plane programs 
 T=(V T , E T ): a node in V T is an MAT; an edge in E T is an MAT dep L2/L3 routing program Bene+it#1: Handle program diversity Bene+it#2: Ease SPEED analysis on program properties TDG for the program 8 Background | Problems | Challenges | Design | Evaluation | Summary

Program Merging for Resource EfLiciency Motivation#1: Requirement for reducing resource usage 
 Motivation#2: Occurrence of redundant MATs among programs 9 Background | Problems | Challenges | Design | Evaluation | Summary

Program Merging for Resource EfLiciency Motivation#1: Requirement for reducing resource usage 
 Motivation#2: Occurrence of redundant MATs among programs In Software-de+ined Measurement (SDM): Program#1 Program#2 Program#3 for +low count for heavy hitter for anomalies 9 Background | Problems | Challenges | Design | Evaluation | Summary

Program Merging for Resource EfLiciency Motivation#1: Requirement for reducing resource usage 
 Motivation#2: Occurrence of redundant MATs among programs In Software-de+ined Measurement (SDM): Program#1 Program#2 Program#3 for +low count for heavy hitter for anomalies C: CRC hashing B: CRC hashing A: CRC hashing Redundant MATs (3× hashing) 9 Background | Problems | Challenges | Design | Evaluation | Summary

Program Merging for Resource EfLiciency Motivation#1: Requirement for reducing resource usage 
 Motivation#2: Occurrence of redundant MATs among programs In Software-de+ined Measurement (SDM): Program#1 Program#2 Program#3 Program#4 + + = for +low count for heavy hitter for anomalies merge #1-#3 C: CRC hashing B: CRC hashing CRC hashing A: CRC hashing Redundant MATs (3× hashing) (only one hashing) 9 Background | Problems | Challenges | Design | Evaluation | Summary

Program Merging for Resource EfLiciency Algorithm based on longest common subsequence (LCS) 
 Input : n TDGs Output : a compound TDG, T m WorkLlow : n-1 iterations; each iteration takes 2 TDGs to merge 10 Background | Problems | Challenges | Design | Evaluation | Summary

b 1 b 2 b 4 a 1 a 2 a 3 b 3 b 5 (a) TDG T 1 (b) TDG T 2 11

b 1 b 2 b 4 a 1 a 2 a 3 a 1 a 2 a 3 b 3 b 5 b 1 b 2 b 3 b 4 b 5 (a) TDG T 1 (b) TDG T 2 (c) Topological Orderings a 1 b 1 a 2 b 3 a 3 b 4 (d) Pairs of 
 Redundant MATs 11

b 1 b 2 b 4 a 1 a 2 a 3 a 1 a 2 a 3 b 3 b 5 b 1 b 2 b 3 b 4 b 5 (a) TDG T 1 (b) TDG T 2 (c) Topological Orderings a 1 b 1 a 1 a 2 a 3 a 2 b 3 b 1 b 2 b 3 b 4 b 5 a 3 b 4 (e) Longest Common 
 (d) Pairs of 
 Subsequence (LCS) Redundant MATs 11

b 1 b 2 b 4 a 1 a 2 a 3 a 1 a 2 a 3 b 3 b 5 b 1 b 2 b 3 b 4 b 5 (a) TDG T 1 (b) TDG T 2 (c) Topological Orderings a 1 c 1 b 2 c 3 b 1 a 1 a 2 a 3 a 2 b 3 c 2 b 1 b 2 b 3 b 4 b 5 a 3 b 4 b 5 (e) Longest Common 
 (f) Merging T 1 and T 2 
 (d) Pairs of 
 Subsequence (LCS) into TDG T m Redundant MATs 11

One Big Switch (OBS) Abstraction To place T m , SPEED abstracts substrate network as an OBS 
 (1) Separate heterogeneous constraints in two phases (2) In each phase, only consider one objective 
 Bene+it#1: Simplify program deployment Bene+it#2: Achieve multi-objective deployment S1 (4 stages) S2 (4 stages) 12 Background | Problems | Challenges | Design | Evaluation | Summary