Varying-Speed Multiprocessors Zhishan Guo and Sanjoy Baruah - - PowerPoint PPT Presentation

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Varying-Speed Multiprocessors Zhishan Guo and Sanjoy Baruah - - PowerPoint PPT Presentation

Oct 24, 2022 750 likes •1.13k views

Mixed-Criticality Scheduling upon Varying-Speed Multiprocessors Zhishan Guo and Sanjoy Baruah Department of Computer Science, UNC Chapel Hill Outline Motivation Model & Previous Work Algorithm and Discussion Conclusion and

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Mixed-Criticality Scheduling upon Varying-Speed Multiprocessors

Zhishan Guo and Sanjoy Baruah Department of Computer Science, UNC Chapel Hill

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SLIDE 2

Outline

  • Motivation
  • Model & Previous Work
  • Algorithm and Discussion
  • Conclusion and further work
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SLIDE 3

Outline

  • Motivation
  • Model & Previous Work
  • Algorithm and Discussion
  • Conclusion and further work
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SLIDE 4

Motivation

  • Mixed-Criticality (MC)

– Jobs with different importance levels are more likely to be implemented on a common platform

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SLIDE 5

Motivation

  • Mixed-Criticality (MC) arises from:

– Different estimations to job’s true WCET leads to multiple WCET for each job.

ciLO ciHI t NP-Hard

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SLIDE 6

Motivation

  • Mixed-Criticality (MC) also arises from

– The precise speed of the processor upon which the system is implemented varies during runtime, and estimates must be made about how low the actual speed may fall.

t sn s Processor speed s(t)

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SLIDE 7

Previous Work

  • On Mixed-Criticality (MC) Scheduling that arises from

varying-speed property of the processor

  • Job Set + Non-monitored case:
  • NP-hard with 1.618 speed up factor [SIES2013].
  • Job Set + Self-monitoring case:
  • LP-based optimal solution [RTSS2013];
  • Time complexity reduced to O(n2) [in submission];
  • Multi-WCET + V.-Speed Processor [in submission].
  • Implicit Sporadic Task Set [RTSS2014].

Self-monitoring: the system “immediately” knows its execution speed during runtime.

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SLIDE 8

Motivation

Hardware Design Varying Processor Speed

Recover late signals (at circuit level) by delaying the next clock tick

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SLIDE 9

Motivation

Hardware Design Varying Processor Speed

Globally Asynchronous Locally Synchronous (GALS) processors

  • Extremely energy efficient and fast
  • Highly non-deterministic
  • More use in safety-critical embedded systems
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SLIDE 10

Motivation

Hardware Design Ambient Temperature Varying Processor Speed

Temperature Changing Linux: cpuspeed

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SLIDE 11

Motivation

Hardware Design Ambient Temperature Varying Processor Speed Work Load + Battery Strength

Dynamic Freq. Scaling

Lightly-Loaded Processors Clock Rates (voltage) Reducing

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Outline

  • Motivation
  • Model & Previous Work
  • Algorithm and Discussion
  • Conclusion and further work
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SLIDE 13

Model - Varying-Speed Processors

t s Normal mode Degraded mode

  • Normal mode vs Degraded mode

sn=1 Processor speed s(t)

Degraded mode: Computing capabilities are diminished.

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Problem - For a Two-level Case

  • Given a job set & varying speed processors,

we would like to construct a correct schedule that: Criticality Level Normal mode Degraded mode HI jobs LO jobs

It is not a priori known when, or whether, such degradation will occur (non-clairvoyant).

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Previous - Linear Programming

  • To construct the table S := xi,j (≥ 0)

– amount of execution assign to job Ji in interval Ij

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SLIDE 16

Ji Ji

Previous - Linear Programming

  • Constraints to construct S:= xi,j ≥ 0

– Each job receives adequate execution under normal circumstances

t

Ji s(t) J? J?

ai di

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SLIDE 17

J?

Previous - Linear Programming

  • Constraints to construct S := xi,j ≥ 0

– Each job receives adequate execution (normal) – The capacity of each interval is respected

t

Ji ai di J? J? a? J? J? Ji s(t)

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SLIDE 18

Previous - Linear Programming

  • Constraints to construct S := xi,j ≥ 0

– Each job receives adequate execution (normal) – The capacity of each interval is respected – Degradation at any time should not cause a HI-critilicality job miss its deadline

Ji Ji

tm

Ji s(t)

tl

J? J? J?

s

d

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SLIDE 19

Uniprocessor - An Example

sn = 2 sd = 1

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 1 JHI2 1 1

S

I ai ci di χi JLO 2 2 LO JHI1 2 3 HI JHI2 2 4 HI

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SLIDE 20

JHI2

Uniprocessor - An Example

sn = 2 sd = 1

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 1 JHI2 1 1

S

I ai ci di χi JLO 2 2 LO JHI1 2 3 HI JHI2 2 4 HI

t 2 4

s(t) JLO JHI1 JHI

1

JHI

2

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Outline

  • Motivation
  • Model & Previous Work
  • Algorithm and Discussion
  • Conclusion and further work
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For Multiprocessor…

  • More constraints need to be added…

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 1 JHI2 1 1

S

I ai ci di χi JLO 2 2 LO JHI1 2 3 HI JHI2 2 4 HI

t 2 4

s(t) JHI1

t 2 4

s(t) JHI1

m=2 sn = 1 sd = 0.5

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SLIDE 23

For Multiprocessor…

  • More constraints need to be added…

m=2 sn = 1 sd = 0.5

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 0.5 0.5 JHI2 1 0.5 0.5

S

I ai ci di χi JLO 2 2 LO JHI1 2 4 HI JHI2 2 4 HI Necessary and Sufficient

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SLIDE 24

For Multiprocessor…

  • Mapping a LP solution to a schedule…

m=2 sn = 1 sd = 0.5

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 0.5 0.5 JHI2 1 0.5 0.5

S

I ai ci di χi JLO 2 2 LO JHI1 2 4 HI JHI2 2 4 HI

t 2 4

s(t)

1

t 2 4

s(t)

2

JLO

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SLIDE 25

2

For Multiprocessor…

  • Mapping a LP solution to a schedule…

m=2 sn = 1 sd = 0.5

Intervals [0,2) [2,3) [3,4) JLO 2 JHI1 1 0.5 0.5 JHI2 1 0.5 0.5

S

I ai ci di χi JLO 2 2 LO JHI1 2 4 HI JHI2 2 4 HI

t 2 4

s(t)

1

t 2 4

s(t) J

L O

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For Multiprocessor…

  • We now have m processors instead of one…
  • Degraded mode (Wrap-Around MC)
  • A system with m processors is in degraded mode at a given

instant t if there exists at least one processor executing at the speed in the range of [s,1).

  • Weak Degraded mode (Level MC)
  • A system with m processors is in weak degraded mode at a

given instant t if the average executing speed is in the range

  • f [s,1).
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Outline

  • Motivation
  • Model & Previous Work
  • Algorithm and Discussion
  • Conclusion and further work
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Conclusion

  • Model

– Uniprocessor -> Multiprocessor Platforms with varying-speed performance during run-time

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Conclusion

  • Model

– Uniprocessor -> Multiprocessor Platforms with varying-speed performance during run-time

  • Algorithm

– Based on Linear Programming – Two optimal algorithms under two definitions of degraded mode – Show necessity of processer sharing

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Conclusion

Hardware Design Ambient Temperature Varying Processor Speed Work Load + Battery Strength

Wireless Network

Data Communication (bandwidth)

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Further Work

  • Efficiency improvements

– LP Polynomial -> O(m2n2) – Proc Sharing (Quantum)

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SLIDE 32

Further Work

  • Efficiency improvements
  • Limited Preemption & Migration
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Further Work

  • Efficiency improvements
  • Limited Preemption & Migration
  • Multiple levels of criticality

– More than two thresholds for processor speeds

t sn sd Processor speed s(t) sf Normal mode Degraded mode Failure mode

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SLIDE 34

Further Work

  • Efficiency improvements
  • Limited Preemption & Migration
  • Multiple levels of criticality
  • Combination with previous models

– Schedule MC instance upon varying-speed processors

I ai ci di χi JLO 0 [1,1] 2 LO JHI 0 [1,2] 4 HI

sn = 1 sd = 0.5

t 2 4

s(t) JLO JHI

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SLIDE 35

Thank you!

Zhishan Guo zsguo@cs.unc.edu

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Relationship with prior work

  • Mixed-Criticality task model (previous works)
  • Ji - (ai, di, [ciHI, ciLO], χi)
  • Execution speed = 1
  • Our model
  • Ji - (ai, di, ci, χi), sn, s
  • E.g.,

ciLO ciHI t ci t ? t s(t) 1 0.5 ci

ci/sd

t 1 0.5 ci s(t)

ci/sn

t 1 0.5 ci s(t)

A slower processor can be transformed into longer WCET