Tomorrows Exascale Systems: Not Just Bigger Versions of Todays Peta - - PowerPoint PPT Presentation
Tomorrows Exascale Systems: Not Just Bigger Versions of Todays Peta -Computers Thomas Sterling Professor of Informatics and Computing, Indiana University Chief Scientist and Associate Director Center for Research in Extreme Scale
Thomas Sterling
Professor of Informatics and Computing, Indiana University Chief Scientist and Associate Director
Center for Research in Extreme Scale Technologies (CREST) School of Informatics and Computing Indiana University
November 20, 2013
NUDT and Inspur for National Supercomputer Center in Guangzhou
– 16,000 nodes contain 32,000 Xeon Ivy Bridge processors and 48,000 Xeon Phi accelerators totaling 3,120,000 cores – 162 cabinets in 720m2 footprint – Total 1.404 PB memory (88GB per node) – Each Xeon Phi board utilizes 57 cores for aggregate 1.003 TFLOPS at 1.1GHz clock – Proprietary TH Express-2 interconnect (fat tree with thirteen 576-port switches) – 12.4 PB parallel storage system – 17.6MW power consumption under load; 24MW including (water) cooling – 4096 SPARC V9 based Galaxy FT-1500 processors in front-end system
0.1 1 10 100 1000 10000 100000 1000000 10000000 100000000 1E+09 1E+10 1E+11 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
SUM N=1 N=500 1 Gflop/s 1 Tflop/s
100 Mflop/s 100 Gflop/s 100 Tflop/s 10 Gflop/s 10 Tflop/s
1 Pflop/s
100 Pflop/s 10 Pflop/s
1 Eflop/s
Courtesy of Erich Strohmaier LBNL
Complex Multi-scale, Multi-physics Processes
Courtesy of Bill Tang, Princeton
GTC simulation Computer name PE# used Speed (TF) Particle # Time steps Physics Discovery (Publication) 1998
Cray T3E NERSC 102 10-1 108 104 Ion turbulence zonal flow (Science, 1998)
2002
IBM SP NERSC 103 100 109 104 Ion transport scaling (PRL, 2002)
2007
Cray XT3/4 ORNL 104 102 1010 105 Electron turbulence (PRL, 2007); EP transport (PRL, 2008)
2009
Jaguar/Cray XT5 ORNL 105 103 1011 105 Electron transport scaling (PRL, 2009); EP-driven MHD modes
2012-13
(current)
Cray XT5Titan ORNL Tianhe-1A (China) 105 104 1012 105 Kinetic-MHD; Turbulence + EP + MHD
2018
(future)
To Extreme Scale HPC Systems 106 1013 106 Turbulence + EP + MHD + RF
Progress in Turbulence Simulation Capability: Faster Computer Achievement of Improved Fusion Energy Physics Insights
* Example here of GTC code (Z. Lin, et al.) delivering production runs @ TF in 2002 and PF in 2009
Courtesy of Bill Tang, Princeton
6
machine)
– Semantics, Mechanisms, Policies, Parameters, Metrics – Driven by technology opportunities and challenges – Historically, catalyzed by paradigm shift
– For reasoning towards optimization of design and
– Architecture, runtime and OS, programming models – Reduces design complexity from O(N2) to O(N)
– Enables holistic reasoning about concepts and tradeoffs
– Establishes a phylum of HPC class systems
Vector Model 1975 SIMD-array Model 1983 CSP Model 1991 SIF-MOE Model 1968 Von Neumann Model 1949
? Model 2020
1 2 3 4 5 6 7 8 9 10 1/1/1992 1/1/1996 1/1/2000 1/1/2004 1/1/2008 1/1/2012 Power (MW) Heavyweight Lightweight Heterogeneous
Courtesy of Peter Kogge, UND
9
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1/1/1992 1/1/1996 1/1/2000 1/1/2004 1/1/2008 1/1/2012 TC (Flops/Cycle) Heavyweight Lightweight Heterogeneous
Courtesy of Peter Kogge, UND
– Insufficiency of concurrency of work – Impacts scalability and latency hiding – Effects programmability
– Time measured distance for remote access and services – Impacts efficiency
– Critical time additional work to manage tasks & resources – Impacts efficiency and granularity for scalability
– Delays due to simultaneous access requests to shared physical or logical resources
P – performance (ops) e – efficiency (0 < e < 1) s – application’s average parallelism, a – availability (0 < a < 1) U – normalization factor/compute unit E – watts per average compute unit r – reliability (0 < r < 1)
programming methods, and runtime
– Latency mitigating architectures
(dispatch)
for dynamic load balancing
continuous optimization
replication, and local adaptation for global optima in time and space
– Divides work into smaller tasks – Increases concurrency
– Move work to data – Keeps work local, stops blocking
– Declarative criteria for work – Event driven – Eliminates global barriers
– Merger of flow control and data structure
– Global address space – Simplifies random gathers
– Lightweight threads for additional level of parallelism – Lightweight threads with rapid context switching for non-blocking – Low overhead for finer granularity and more parallelism – Parallelism discovery at runtime through data-directed execution – Overlap of successive phases of computation for more parallelism
– Lightweight thread context switching for non-blocking – Overlap computation and communication to limit effects – Message-driven computation to reduce latency to put work near data – Reduce number and size of global messages
– Eliminates (mostly) global barriers – However, ultimately will require hardware support in the limit – Uses synchronization objects exhibiting high semantic power – Reduces context switching time – Not all actions require thread instantiation
– Adaptive resource allocation with redundant resources
– Eliminates polling and reduces # of sources of synch contacts
– Complexes (ParalleX Threads) and ParalleX Thread Management – Parcel Transport and Parcel Management – Local Control Objects (LCOs) – Active Global Address Space (AGAS)
MPI HPX Computational phases for LULESH (mini-app for hydrodynamics codes). Red indicates work White indicates waiting for communication Overdecomposition: MPI used 64 process while HPX used 1E3 threads spread across 64 cores.