The Time-predictable Multicore Architecture T-CREST Martin - - PowerPoint PPT Presentation

The Time-predictable Multicore Architecture T-CREST

Martin Schoeberl Technical University of Denmark

New Architectures Needed

n Design a computer architecture for real-time systems

t Worst-case execution time (WCET) is the main design constraint t Average-case performance not (so) interesting

n Use and develop features that are

t WCET analysis driven t Have a low WCET

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Time-predictable Computer Architecture

n Common computer architecture wisdom

Make the common case fast and the uncommon case just correct

n Time-predictable computer architecture

Make the worst case fast and the whole system analyzable

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T-CREST Architecture

n Chip-multiprocessor for high performance

t Target: 64 cores in an FPGA

n Time-predictable

t Processor t Network-on-Chip (NoC) t Local memory (SPM, $) t SDRAM controller

n Integration in WCET analysis n Compiler support for WCET analysis

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T-CREST Outcome

n Provide a complete platform

t Hardware in an FPGA t Supporting compiler and analysis tool

n Resulting designs in open source

t BSD license t Simplifies cooperation

n Up to compiler

t No operating system research t No Model of Computation research t No automatic parallelization research

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T-CREST Chip

Patmos

Dec M$ + SPM S/D$

NI Patmos

Dec M$ + SPM S/D$

NI R Patmos

Dec M$ + SPM S/D$

NI R

Memory Tree Memory Controller SDRAM Memory

R

Platform - Hardware

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Platform - Software

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T-CREST Partners

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Processor

n Time-predictable processor

t Written in Chisel

n Called Patmos n Flexibility to define the instruction set

t A compiler is adapted for Patmos at TUV

n Co-design for low WCET of

t Patmos t Compiler t WCET analysis

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Patmos

n A research platform for real-time architecture (e.g. caches, SPM) n RISC style microprocessor n Dual issue VLIW n Full predication – all instructions n Split caches

t Scratchpad memory (SPM) t Stack cache t Data cache t Method cache

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Pipeline Overview

RF M$ IR PC + Dec S$ SP D$ RF + Fetch Decode Execute Memory Writeback Martin Schoeberl 11 T-CREST

Patmos WCET Features

n No timing anomaly

t As far as I know ;-)

n Constant execution time of instructions n 0 timing dependency between instructions

t All caches miss in the same pipeline stage t Load/use dependency scheduled by the compiler

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Compiler

n Adaption of LLVM n Full support of Patmos ISA n Support for stack cache instructions

t Reserve, free, ensure

n Support for method cache n Optimize for WCET

t Integration with AbsInt aiT tool t Delivers flow facts for aiT t Single-path code generation

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Network on Chip (NoC)

n Two types of traffic:

t Processor to processor

• DMA driven block transfers SPM → SPM

(message passing)

• Nature: All-to-all

t Processor to shared memory (SDRAM)

• Arbitration in NOC and in memory controller
• Nature: All-towards-one

n Globally-Asynchronous Locally-Synchronous (GALS) implementation of platform

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NoC Centric View

NI NI NI NI NI NI Clock domain Clock domain Mesochronous NIs Asynchronous

• Packet switched
• TDM based

Read/write memory-style interface

The NOC

CPU $

SPM

CPU $

SPM

CPU $

SPM

CPU $

SPM

CPU $

SPM

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CPU $

SPM

Real-Time Guarantees

n NoC is a shared communication medium n Needs arbitration

t Time-division-multiplexing is predictable

n Message latency/bandwidth depends on

t Schedule t Topology t Number of nodes

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Argo – the T-CREST NoC

n TDM based NoC – statically scheduled n Different packet sizes possible n 3 stage pipelined router

t Synchronous and asynchronous

n Network interface (NI)

t Ticks at TDM clock (mesochronous)

• Drives the asynchronous network

t Time shared DMA machinery t SPM for clock domain crossing

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A TDM-based Router

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HPU HPU HPU

. . . . . . . . . . . .

X bar

Route flit flit Header Payload Link Link Link Link Link Link

Network Interface for Argo

Traditional NI design Argo micro-architecture

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Argo NI Key Features

n SPM used for clock domain crossing n One DMA needed per connection n But only one active at any given time due to TDM

t Enables efficient table-based implementation of DMA controllers

n End-to-end (i.e., SPM-to-SPM) data transfer

t Avoids buffering and flow control

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Distributed TDM Memory NoC

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Multicore Memory controller Memory NI Processor core Processor core MI NI NI Processor core Processor core NI OCP OCP

TDM Tree

n The TDM schedule at the memory interface

t No buffering in the memory controller

n Pipelined tree and response channel n Pipeline delay in tree is known

t No buffering in tree nodes

n Distributed TDM arbitration at nodes

t Just with the right offset t The packet knows when to go

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WCET Analysis

n Adaption of AbsInt aiT tool n Support of Patmos ISA

t Predicated instructions t Dual-issue pipeline

n Simple method cache analysis n Stack cache analysis n Integration with compiler

t platin

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Software and Tools

n Operating systems (single core)

t RTEMS t ARINC 653 OSPAT

n Operating system multi-core

t MOSSCA from Augsburg

n NoC schedule generator n NoC user library n Two use cases from industry partners for platform evaluation

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Using T-CREST

n Open source

t Industry friendly BSD license

n Hosted at GitHub

t https://github.com/t-crest t You can join the team and get write access

n Only (mostly) free tools used n Public mailing list patmos-processor at Yahoo n http://patmos.compute.dtu.dk/

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FPGA Platforms

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Simulation (SW)

n Processor simulation

t SW simulator t HW based emulator

n LLVM compiler n Just your laptop

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Simulation (HW)

n Processor simulation

t HW based emulator t Free wave viewer

n Multicore simulation

t ModelSim, license for multi language

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The Real Thing - Hardware

n Full T-CREST execution

t 9 cores

n On $ 300 FPGA board n Only free tools needed

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Future Work

n EC project finished

t Continue with DK funded project PREDICT

n We will keep the T-CREST name n Platform for future EC funded projects n Immediate next steps

t Programming models t Full system simulator (C++) t Integration with SWEET (platin)

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The T-CREST Team

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Want to Learn at SYCHRON

n How to program T-CREST n We need a programming model

t That includes computation and communication

n Maybe synchronous languages would fit n Support for multicore processor

t Using message passing NoC

n Let’s team up

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Summary

n We need new computer architecture for real-time systems n WCET analyzability is of primary importance n T-CREST is a platform

t Processor, NoC, memory controller, compiler, WCET analysis

n Technology is mostly open source n https://github.com/t-crest

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