State-of-the-art Multicore Debugging and Tracing concepts by - - PowerPoint PPT Presentation

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State-of-the-art Multicore Debugging and Tracing concepts by - - PowerPoint PPT Presentation

Aug 05, 2023 182 likes •392 views

State-of-the-art Multicore Debugging and Tracing concepts by Alexander Merkle, Lauterbach GmbH State-of-the-art Multicore Debug & Trace Alexander Merkle 2013 / 11 / 14 www.lauterbach.com 1 / 20 Agenda AMP or SMP introduction

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 1 / 20

State-of-the-art Multicore Debugging and Tracing concepts

by Alexander Merkle, Lauterbach GmbH

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 2 / 20

Agenda

AMP or SMP introduction

 Debug

 Hardware aspects for off-chip debug  Operating system points of view

 Trace

 Hardware aspects for off-chip trace  Trace timestamping

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 3 / 20

AMP – Asymmetric MultiProcessing Software

Incompatible

  • Architecture
  • Instruction Set
  • Endianness

... A1 B1

Hardware

AMP

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 4 / 20

Software

Set of cores Type A Set of cores Type B

Hardware

A1 B1

AMP – Asymmetric MultiProcessing

Incompatible

  • Architecture
  • Instruction Set
  • Endianness

...

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 5 / 20

Hardware Software

Set of cores Type A Set of cores Type B A1 A2 A3 B1 B2 B3 Core Assignment

SMP – Symmetric MultiProcessing

Incompatible

  • Architecture
  • Instruction Set
  • Endianness

...

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 6 / 20

Software

Set of cores Type A Set of cores Type B B1 B2 B3 A1 A2 A3

Hardware

Core Assignment

SMP – Symmetric MultiProcessing

Incompatible

  • Architecture
  • Instruction Set
  • Endianness

...

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 7 / 20

Software

Set of cores Type A Set of cores Type B AMP A1 A2 A3 B1 B2 B3 SMP-OS

Hardware

Core Assignment

Mixed SMP and AMP configuration

Incompatible

  • Architecture
  • Instruction Set
  • Endianness

... SMP-OS

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 8 / 20

Agenda

 AMP or SMP introduction

Debug

 Hardware aspects for off-chip debug  Operating system points of view

 Trace

 Hardware aspects for off-chip trace  Trace timestamping

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 9 / 20

Software

Set of cores Type A Set of cores Type B

Debugger

Incompatible Architecture Endianness ... AMP A1 A2 A3 B1 B2 B3

Hardware

Core Assignment

AMP or SMP – the offchip debuggers Point of View

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 10 / 20

Core Level Access Architecture Level Access Chip Level Access Debug Port Debug Toolchain

AMP or SMP – the offchip debuggers Point of View

MPSoC Communication Bottleneck (sequential access)

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SLIDE 11

State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 11 / 20

SMP – the System Point of View

The SMP-Operating-System (OS) dispatches TASKs to COREs.

As all cores are equal the core to which the task is dispatched is dynamic.

In case of SMP we need to look to the SMP-SYSTEM in total

Debug features must be synchronous to the whole SMP-SYSTEM → debugging must be synchronous on all cores → onchip hardware assistance for synchronous Go/Break required

The external debug tool needs to be aware of the OS and the OS core assignment.

dispatch to one

  • f the SMP-System
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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 12 / 20

Core Level Access Architecture Level Access Chip Level Access Debug Port Debug Toolchain

AMP or SMP – the offchip debuggers Point of View

Software MPSoC Communication Bottleneck (sequential access) . . . . Core Assignment

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 13 / 20

AMP / SMP debug concept

SMP or AMP

AMP SMP Multiple TRACE32 PowerView instances Single TRACE32 PowerView instance

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 14 / 20

Agenda

 AMP or SMP introduction  Debug

 Hardware aspects for off-chip debug  Operating system points of view

Trace

 Hardware aspects for off-chip trace  Trace timestamping

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 15 / 20

Offchip Trace - Introduction

Logical core number

  • 1. execute
  • 3. Compress Instruction Flow to Trace-Stream
  • 2. Instruction-Flow == executed code

Goal: reconstruct the Instruction-Flow of both cores execute

  • 4. Interleaved

Stream 1&2

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 16 / 20 

Challenge: Trace data is interleaved among all cores of the chip. => Timing information is lost.

Δt

Trace - Timestamping

Signal Processing

  • Ext. Timestamping

Recording Transfer HOST

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 17 / 20

Trace - Timestamping

Challenge: Trace data is interleaved among all cores of the chip. => Timing information is lost.

Goal:

Reconstruct original „internal“ concurrent trace streams

Correlate the concurrent trace streams

Using either or a mixture of

Assembly level runtime interpolation

Chip global timestamps

Cycle accurate traces

Problem:

Bandwidth

Bandwidth Accuracy

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 18 / 20

Trace - Outlook

Parallel to Serial

Low lane count with high bandwidth.

Not only in High-Performance but also in Mid-Range (Realtime) market.

Reuse of standard peripherals like USB, PCI-Express, SATA

Challenges:

trace port is no longer optimized according to it's use-case

System Traces

Instrusive but selective trace of data (software based)

Higher-level evaluation, protocol dependent

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 19 / 20

Conclusion

 Multiprocessor systems use symmetric &

asymmetric configurations

 Debugging challenges

 Target operating system  Chip/core level synchronization (Go/Break)  Debug port bottleneck

 Trace challenges

 Trace stream correlation/timestamping  Trace port bandwidth

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State-of-the-art Multicore Debug & Trace ▪ Alexander Merkle ▪ 2013 / 11 / 14 www.lauterbach.com ▪ 20 / 20

Thank you for your Attention Questions?