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Reactive Synthesis Swen Jacobs <swen.jacobs@iaik.tugraz.at> - PowerPoint PPT Presentation

Reactive Synthesis Swen Jacobs <swen.jacobs@iaik.tugraz.at> VTSA 2013 Nancy, France 24.09.2013 u www.iaik.tugraz.at 2 End of Synthesis, Part I: Basics Synthesis as a Game General : LTL Synthesis Time-Efficient : GR(1)


  1. Reactive Synthesis Swen Jacobs <swen.jacobs@iaik.tugraz.at> VTSA 2013 Nancy, France 24.09.2013 u www.iaik.tugraz.at

  2. 2 End of Synthesis, Part I: Basics  Synthesis as a Game  General : LTL Synthesis  Time-Efficient : GR(1) Synthesis  Application : AMBA Bus Protocol  Space-Efficient : Bounded/Safraless Approaches VTSA 2013 Swen Jacobs

  3. 3 Synthesis, Part II: Advanced Topics  Lazy Synthesis  Distributed Synthesis  Parameterized Synthesis  Quantitative Specifications  Robustness VTSA 2013 Swen Jacobs

  4. 4 Lazy Synthesis VTSA 2013 Swen Jacobs

  5. Lazy Synthesis [VMCAI12] 5  Based on SMT-based Bounded Synthesis  Idea : instead of full translation to SMT, use lazy encoding in abstraction refinement approach  Integrates model checking approach to test candidate models and obtain counterexamples VTSA 2013 Swen Jacobs

  6. Lazy Synthesis: Overview 6 VTSA 2013 Swen Jacobs

  7. Partial Design 7  Part of system already implemented  Other part to be synthesized  Interface of processes given VTSA 2013 Swen Jacobs

  8. Lazy Synthesis: Overview 8 Outer Loop : Search for implementation of size 𝑜 , increment 𝑜 if  unrealizability is proved Synthesis Loop : For a given bound 𝑜 : 1. SOLVE: check satisfiability of constraints, obtain candidate implementation 2. CHECK: model check candidate and white-box with monitor automata 3. REFINE: if errors are reachable, construct constraints excluding error paths VTSA 2013 Swen Jacobs

  9. Lazy Synthesis: Solve Phase 9  Transition relation represented as function 𝑢𝑠𝑏𝑜𝑡: 𝔺 𝐽 × ℕ → ℕ , Outputs as functions of type ℕ → 𝔺   Initial constraints : size constraint, initial state  More constraints are added in subsequent calls  Check satisfiability of constraints and obtain model VTSA 2013 Swen Jacobs

  10. Lazy Synthesis: Check Phase 10 Translate assumptions & guarantees to safety automata Assumption: 𝐇𝐆 𝑆𝐹𝐵𝐸𝑍 Guarantee: 𝐇 𝐶𝑉𝑇𝑆𝐹𝑅𝑗 → 𝐆 𝑁𝐵𝑇𝑈𝐹𝑆 = 𝑗 Restriction to safety depends on size bound VTSA 2013 Swen Jacobs

  11. Lazy Synthesis: Check Phase 11  Model-check candidate + white-box + automata  If errors found, call Refine phase, otherwise candidate model satisfies full spec VTSA 2013 Swen Jacobs

  12. Lazy Synthesis: Refine Phase 12  If model checker finds errors, encode them into SMT constraints, forbid them  In BDD-based implementation, we can obtain tree of all error ∈? 𝐅𝟑 ∈ 𝐅𝟑 ∈ 𝐅𝟑 ∈ 𝐅𝟑 ∉ 𝐅𝟑 paths of minimum length  this tree can be translated into a constraint that forbids ∈? 𝐅𝟐 all minimal errors ∈? 𝐅𝟏 VTSA 2013 Swen Jacobs

  13. Lazy Synthesis: Refine Phase 13  Error tree translated to constraint that forbids all error paths , restricted to interface of black-box  For every path, the constraint expresses that at least one output needs to be different VTSA 2013 Swen Jacobs

  14. Lazy Synthesis: Overview 14 Outer Loop : Search for implementation of size 𝑜 , increment 𝑜 if  unrealizability is proved Synthesis Loop : For a given bound 𝑜 : 1. SOLVE: check satisfiability of constraints, obtain candidate implementation 2. CHECK: model check candidate and white-box with monitor automata 3. REFINE: if errors are reachable, construct constraints excluding error paths VTSA 2013 Swen Jacobs

  15. Lazy Synthesis: AMBA Case Study 15 Reconsider AMBA case study, with partial implementation for deterministic parts: “ The arbiter indicates which bus master is currently the highest priority [...] by asserting the appropriate GRANTi signal. When the current transfer completes, as indicated by READY HIGH, then [...] the arbiter will change the MASTER[3:0] signals to indicate the bus master number.” [AMBA Specification (Rev 2.0), ARM Ltd.] VTSA 2013 Swen Jacobs

  16. Lazy Synthesis: AMBA Case Study 16 Other statements translated to LTL : “The arbitration mechanism is used to ensure that only one master has access to the bus at any one time.” ∀𝑗 ≠ 𝑘: 𝐇 𝑆𝐹𝐵𝐸𝑍 → ¬ 𝐻𝑆𝐵𝑂𝑈𝑗 ∧ 𝐻𝑆𝐵𝑂𝑈𝑘 Some statements modeled with auxiliary variables : “Normally the arbiter will only grant a different bus master when a burst is completing .” ∀𝑗: 𝐇 ¬𝐸𝐹𝐷𝐽𝐸𝐹 → 𝐻𝑆𝐵𝑂𝑈𝑗 ↔ 𝐘 𝐻𝑆𝐵𝑂𝑈𝑗 ( 𝐸𝐹𝐷𝐽𝐸𝐹 defined s.t. it is high when a burst completes) VTSA 2013 Swen Jacobs

  17. Lazy Synthesis: AMBA Case Study 17  AMBA with partial implementation for deterministic parts  crucial part synthesized: arbiter VTSA 2013 Swen Jacobs

  18. AMBA: Bounded size of implementations 18 Synthesis time still grows (double) exponentially! 1400 1200 KS 1000 Circuit size cofactors 800 new spec 600 manual 400 bounded/lazy 200 0 1 2 3 4 5 6 7 8 9 10 #masters More recent results go up to 16 masters VTSA 2013 Swen Jacobs

  19. AMBA: Bounded size of implementations 19 Synthesis time still grows (double) exponentially! bounded/lazy VTSA 2013 Swen Jacobs

  20. Lazy Synthesis: Challenges 20  SMT solving incremental, but Model Checking restarted every time  deep integration of incremental model checking?  interface and safety abstraction currently given by hand  automatically minimize interface?  automatic safety abstraction, or use liveness model checker?  Parallelize?  Extend to distributed case? VTSA 2013 Swen Jacobs

  21. 21 Distributed Synthesis VTSA 2013 Swen Jacobs

  22. Why Distributed Synthesis? 22  Many interesting systems are distributed:  multi-threaded programs  multi-core processors  communication protocols  distributed control  …  Both a prerequisite and a motivation for parameterized synthesis VTSA 2013 Swen Jacobs

  23. Distributed Synthesis 23  Several processes, each decides about subset of outputs  Easy case : all processes have full information; this reduces to standard synthesis problem  How so?  Every process has all inputs, but only subset of outputs  In worst case, synthesize full system for all processes and throw away unnecessary outputs VTSA 2013 Swen Jacobs

  24. Partial Information 24  Hard case : every process only has limited information about environment (and other processes)  Very hard , but decidable, for some architectures like pipelines VTSA 2013 Swen Jacobs

  25. Partial Information 25  Undecidable if there is an information fork [PnueliRosner90,FinkbeinerSchewe05] VTSA 2013 Swen Jacobs

  26. Partial Information: Bounded Synthesis 26 Semi-decision procedure possible, e.g. based on bounded synthesis. Model distributed systems by projection functions from a global state 𝑢 to local state 𝑒 𝑗 𝑢 of component 𝑗 Partial information then expressed by constraints of the form 𝑒 𝑗 𝑢 = 𝑒 𝑗 𝑢 ′ ∧ 𝐽 ∩ 𝐽 𝑗 = 𝐽 ′ ∩ 𝐽 𝑗 → 𝑒 𝑗 𝜐 𝑢, 𝐽 = 𝑒 𝑗 𝜐 𝑢 ′ , 𝐽 ′ (for every process 𝑗 ) VTSA 2013 Swen Jacobs

  27. 27 Parameterized Synthesis VTSA 2013 Swen Jacobs

  28. Parameterized Synthesis 28 [TACAS12,VMCAI13]  Many specifications are parametric in nature  AMBA, communication protocols, etc. Can we synthesize building blocks for arbitrary size systems? VTSA 2013 Swen Jacobs

  29. Parameterized Synthesis 29 Building blocks:  Distributed synthesis  of uniform processes  Decidability results for parameterized verification  particularly, cutoffs VTSA 2013 Swen Jacobs

  30. Parameterized Verification 30 Parameterized verification is decidable for certain systems Asynchronous System : No global clock, a subset of processes are allowed to make a move in every global step (decided by external scheduler). Token Ring : Processes only communicate by passing single (value-less) token in ring architecture. Always exactly one process is scheduled, except for token passing steps. VTSA 2013 Swen Jacobs

  31. Parameterized Verification 31 Parameterized verification is decidable for certain systems Theorem [EmersonNamjoshi95]: In token rings with fair token passing, a given process implementation satisfies parameterized specification 𝜒 in LTL\X iff it satisfies 𝝌 in a ring of small size : 2 processes for 𝜒 = ∀𝑗: 𝑔 𝑗 Corollary : For parameterized synthesis 3 processes for 𝜒 = ∀𝑗: 𝑔(𝑗, 𝑗 + 1) in token rings, it is sufficient to synthesize a process implementation satisfying 𝜒 in 4 processes for 𝜒 = ∀𝑗, 𝑘: 𝑔 𝑗, 𝑘 a ring of size 2 – 5. 5 processes for 𝜒 = ∀𝑗, 𝑘: 𝑔 𝑗, 𝑗 + 1, 𝑘 VTSA 2013 Swen Jacobs

  32. (Un)Decidability 32 Does decidability of parameterized verification make synthesis decidable ? No , since even for two uniform processes in a token ring, distributed synthesis is undecidable . A reduction result from Clarke et al. [CTTV04] shows that parameterized synthesis for formulas ∀𝑗: 𝜒 𝑗 reduces to synthesis of one process, which is decidable. VTSA 2013 Swen Jacobs

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