u www.iaik.tugraz.at
Reactive Synthesis
24.09.2013 Swen Jacobs <swen.jacobs@iaik.tugraz.at> VTSA 2013 Nancy, France
Reactive Synthesis Swen Jacobs <swen.jacobs@iaik.tugraz.at> - - PowerPoint PPT Presentation
Reactive Synthesis Swen Jacobs <swen.jacobs@iaik.tugraz.at> VTSA 2013 Nancy, France 24.09.2013 u www.iaik.tugraz.at 2 End of Synthesis, Part I: Basics Synthesis as a Game General : LTL Synthesis Time-Efficient : GR(1)
u www.iaik.tugraz.at
24.09.2013 Swen Jacobs <swen.jacobs@iaik.tugraz.at> VTSA 2013 Nancy, France
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Outer Loop:
unrealizability is proved Synthesis Loop: For a given bound ๐:
with monitor automata
construct constraints excluding error paths
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Translate assumptions & guarantees to safety automata Assumption: ๐๐ ๐๐น๐ต๐ธ๐ Guarantee: ๐ ๐ถ๐๐๐๐น๐ ๐ โ ๐ ๐๐ต๐๐๐น๐ = ๐ Restriction to safety depends on size bound
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into a constraint that forbids all minimal errors
โ? ๐ ๐ โ ๐ ๐ โ ๐ ๐ โ ๐ ๐ โ ๐ ๐ โ? ๐ ๐ โ? ๐ ๐
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Outer Loop:
unrealizability is proved Synthesis Loop: For a given bound ๐:
with monitor automata
construct constraints excluding error paths
Reconsider AMBA case study, with partial implementation for deterministic parts: โThe arbiter indicates which bus master is currently the highest priority [...] by asserting the appropriate GRANTi
READY HIGH, then [...] the arbiter will change the MASTER[3:0] signals to indicate the bus master number.โ [AMBA Specification (Rev 2.0), ARM Ltd.]
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Other statements translated to LTL: โThe arbitration mechanism is used to ensure that only one master has access to the bus at any one time.โ โ๐ โ ๐: ๐ ๐๐น๐ต๐ธ๐ โ ยฌ ๐ป๐๐ต๐๐๐ โง ๐ป๐๐ต๐๐๐ Some statements modeled with auxiliary variables: โNormally the arbiter will only grant a different bus master when a burst is completing.โ โ๐: ๐ ยฌ๐ธ๐น๐ท๐ฝ๐ธ๐น โ ๐ป๐๐ต๐๐๐ โ ๐ ๐ป๐๐ต๐๐๐ (๐ธ๐น๐ท๐ฝ๐ธ๐น defined s.t. it is high when a burst completes)
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200 400 600 800 1000 1200 1400 1 2 3 4 5 6 7 8 9 10 KS cofactors new spec manual
#masters Circuit size More recent results go up to 16 masters
bounded/lazy
Synthesis time still grows (double) exponentially!
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Synthesis time still grows (double) exponentially!
bounded/lazy
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checker?
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and throw away unnecessary outputs
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Semi-decision procedure possible, e.g. based on bounded synthesis. Model distributed systems by projection functions from a global state ๐ข to local state ๐๐ ๐ข of component ๐ Partial information then expressed by constraints of the form ๐๐ ๐ข = ๐๐ ๐ขโฒ โง ๐ฝ โฉ ๐ฝ๐ = ๐ฝโฒ โฉ ๐ฝ๐ โ ๐๐ ๐ ๐ข, ๐ฝ = ๐๐ ๐ ๐ขโฒ, ๐ฝโฒ (for every process ๐)
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Can we synthesize building blocks for arbitrary size systems?
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Parameterized verification is decidable for certain systems
Asynchronous System: No global clock, a subset of processes are allowed to make a move in every global step (decided by external scheduler). Token Ring: Processes only communicate by passing single (value-less) token in ring architecture. Always exactly one process is scheduled, except for token passing steps.
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Parameterized verification is decidable for certain systems
Theorem [EmersonNamjoshi95]: In token rings with fair token passing, a given process implementation satisfies parameterized specification ๐ in LTL\X iff it satisfies ๐ in a ring of small size: 2 processes for ๐ = โ๐: ๐ ๐ 3 processes for ๐ = โ๐: ๐(๐, ๐ + 1) 4 processes for ๐ = โ๐, ๐: ๐ ๐, ๐ 5 processes for ๐ = โ๐, ๐: ๐ ๐, ๐ + 1, ๐ Corollary: For parameterized synthesis in token rings, it is sufficient to synthesize a process implementation satisfying ๐ in a ring of size 2 โ 5.
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Does decidability of parameterized verification make synthesis decidable? No, since even for two uniform processes in a token ring, distributed synthesis is undecidable. A reduction result from Clarke et al. [CTTV04] shows that parameterized synthesis for formulas โ๐: ๐ ๐ reduces to synthesis of one process, which is decidable.
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Bounded synthesis encoding with following extensions:
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Can synthesize distributed arbiter in token ring of 4 processes with spec โ๐: ๐ป ๐
๐ โ ๐บ๐๐
โ๐ โ ๐: ยฌ ๐๐ โง ๐๐ This takes Z3 about 10 sec. But: problem gets hard very fast. For extended spec with โ๐: ยฌ๐๐๐๐
๐ โง ๐ป ๐๐ โ ยฌ๐๐๐๐ ๐ ,
needs about 240 sec.
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๐ โ ๐บ๐๐
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Size of SMT queries: full4: 6MB 0.6MB pnueli4: 21MB 4MB
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be lifted to synthesis
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Arbiter
r0, r1 g0, g1
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Arbiter
r0, r1 g0, g1
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Specification (in LTL): Guarantees:
Assumption:
Arbiter
r0, r1 g0, g1
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Specification (in LTL): Guarantees:
Assumption:
Arbiter
r0, r1 g0, g1
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good (1) bad (0) M2 M1 M3 M4 M1 M2 M3 M4 Set of all words
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good (1) bad (0) M2 M1 M3 M4 M1 M2 M3 M4
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good (1) bad (0) M2 M1 M3 M4 M1 M2 M3 M4
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bad (0) M2 M1 M3 M4 M1 M2 M3 M4 better >0
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เธ๏ w1 ๏ฝ(rg r g rg)๏ท เธ๏ w2 ๏ฝ(rg r g r g)๏ท เธ๏ w3 ๏ฝ(rg rg rg )๏ท เธ๏ (111)๏ท เธ๏ (001)๏ท เธ๏ (000)๏ท เธ๏ value(w1) ๏ฝ1 เธ๏ value(w2) ๏ฝ 1
3
เธ๏ value(w3) ๏ฝ 0
Arbiter
r0, r1 g0, g1
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What is the value of a system?
Worst-case analysis is natural extension of Boolean case
bad (0) M2 M1 M3 M4 M1 M2 M3 M4 better
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value = value๐ต1 + value๐ต2
2x
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2x
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2x Worst mean-payoff = payoff in minimum mean-payoff cycle
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Classical Specification Construct two player game Solve game Construct system Correct system
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Safety Construct two player game Solve game Construct system Correct system
+ Mean- payoff Mean- payoff Optimal
[EhrenfeuchtMycielski79]
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Arbiter
r0, r1 g0, g1
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Mean payoff game:
value? strategy?
ยฌ๐ ๐ (1) ๐ ๐ (1) ยฌ๐
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Specification (in LTL): Guarantees:
Assumption:
Suppose payoff 1 when no grant is given
Arbiter
r0, r1 g0, g1
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Specification (in LTL): Guarantees:
Assumption:
Worst case: grant in every tick โ payoff 0 Thus, behavior when no requests arrive is irrelevant! Arbiter that behaves best in worst case ๏น best arbiter!
Arbiter
r0, r1 g0, g1
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G(r ๏ฎ g) mininize #g value? worst-case optimal: 0
ยฌ๐ ๐(0) ๐ ๐(0) ยฌ๐(1) ยฌ๐(1)
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๏ขantagonist strategies ๏ฒ, payoff(๏ณ, ๏ฒ) ๏ณ payoff(๏ณโ, ๏ฒ) ๏คantagonist strategy ๏ฒ, payoff(๏ณ, ๏ฒ) > payoff(๏ณโ, ๏ฒ)
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[ChatterjeeHenzingerJurdzinski05]
[BloemChatterjeeHenzingerJobstmann09]
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[GhezziJazayeriMandrioli91] Questions
systems? Very little attention in formal methods
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The air traffic control system must track up to 50 planes. (In that case,) response time must be at most 1 second.
You want graceful degradation! But: digital systems have no natural notion of continuity!
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Response time
[Davis90]
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Specification (in LTL): Guarantees G:
Assumption A:
Arbiter
r0, r1 g0, g1
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Input trace: r1r2 r1 ๐ 2 ๐ Output trace: ๐1๐2 ๐1๐2 ๐ r1r2 r1 ๐ 2 ๐ ๐1๐2 ๐1๐2 ๐
g1g2 g1g2 g1g2 ๏ r1r2 r1 r1r2 r1 M1 g1g2 g1g2 r2 ๏ r1r2 r1r2 r2 r1 r1 ๏ M2
Does not recover from an error! Does recover from an error!
Verification does not distinguish between two systems Synthesis may give you either system
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[SeshiaLiMitra]
Dijkstra]
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Claim: User should decide what is reasonable For arbiter: When two requests come
How do we state what is preferable?
g1 = G(r1 ๏ฎ X g1) ๏ G(r2 ๏ฎ X g2) g2 = G ๏(g1 ๏ g2) a = G ๏(r1 ๏ r2) Spec: a๏ฎ g1 ๏ g2 Arbiter
r0, r1 g0, g1
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Case by case analysis of wrong behavior?
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Response time planes response time (s) ๏ฃ50 1 51 1.1 52 1.2 53 1.3 โฆ โฆ
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r1 r1 r1g1 r1g1 (0) (0) (0) (0) g1 true (1)
G(r1 ๏ฎ X g1)
(1)
Environment error: 0 System error: 0 Environment error: 1 System error: โ
r1 0 1 1 1 1 1 ... r2 0 0 0 0 0 0 ... g1 0 0 1 1 1 1 โฆ g2 1 1 0 0 0 0 โฆ r1 0 1 1 1 1 1 ... r2 0 1 0 0 0 0 ... g1 0 0 0 1 1 1 โฆ g2 1 1 1 0 0 0 โฆ
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r1 r1 r1g1 r1g1 (0) (0) (0) (0) g1(1)
Environment error: 0 System error: 0
r1 0 1 1 1 1 1 ... r2 0 0 0 0 0 0 ... g1 0 0 1 1 1 1 โฆ g2 1 1 0 0 0 0 โฆ similar for
g1 true
Environment error: 1 System error: 1
r1 0 1 1 1 1 1 ... r2 0 1 0 0 0 0 ... g1 0 0 0 1 1 1 โฆ g2 1 1 1 0 0 0 โฆ
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environment and one for the system
system
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g1g2 g1g2 g1g2 ๏ g1g2 g1g2 r1r2 r1 r2 ๏ r1r2 r1r2 r1r2 r2 r1 r1 r1 ๏ M1 M2
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Spec is of the form A ๏ฎ G
environment
Idea: take ratio of system errors to environment errors
planes to excess response time
requests to missed requests
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Response time
Arbiter
r0, r1 g0, g1
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env-err sys-err
d
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Questions:
One solution:
many errors if the system does
and environment faults is at most k.
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[VMCAI12] B. Finkbeiner, S. Jacobs: Lazy Synthesis. VMCAI 12. [PnueliRosner90] A. Pnueli, R. Rosner: Distributed Reactive Systems are Hard to
[FinkbeinerSchewe05] B. Finkbeiner, S. Schewe: Uniform Distributed Synthesis. LICS 05. [TACAS12] S. Jacobs, R. Bloem: Parameterized Synthesis. TACAS 12. [VMCAI13] A. Khalimov, S. Jacobs, R. Bloem: Towards Efficient Parameterized
[EmersonNamjoshi95] E. Emerson, K. Namjoshi: Reasoning about Rings. POPL 95. [EhrenfeuchtMycielski79] A. Ehrenfeucht, J. Mycielski: Positional Strategies for Mean Payoff Games. IJGT 79. [ChatterjeeHenzingerJurdzinski05] K. Chatterjee, T. Henzinger, M. Jurdzinski: Mean- Payoff Parity Games. LICS 05. [BloemChatterjeeHenzingerJobstmann09] R. Bloem, K. Chatterjee, T. Henzinger, B. Jobstmann: Better quality in synthesis through quantitative objectives. CAV 09. [GhezziJazayeriMandrioli91] C. Ghezzi, M. Jazayeri, D. Mandrioli: Software qualities and principles.