Outline • Introduction Core (IP)-Based Design • Challenges • Reusable Components • Communication-Based Design Processors and Architectures for • Platform-Based Design Embedded Systems • Networks On-Chip Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Chip Overview Reuse • # transistors increases 60% / year • Design productivity increases 20% / year • Design gap is growing • Combat by reuse • Reuse by IPRs • Requires new specification, methodolgy and Several millions of transistors available A processor core needs only some hundred K gates tools Several processors fit on one chip Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Forecast Challenges • Core-based design solves all problems? • Maybe, but several challenges remain: – Core description – System description – Core intercommunication – Verification – Production volume Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet 1
Reusable Components Synthesizable Core • Intellectual Property (IP) • High-Level Description (e.g. VHDL or Verilog) • Intellectual Property Rights (IPR) • Functional Verification Completed • Synthesizable Core – Technology Independent • Synthesis is required • Soft Core – Technology Dependent Netlist • Layout is required • Firm Core – Technology Dependent Netlist • Size and Speed not predictable • Hard Core – Fixed Layout Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Soft Core Firm Core • Technology Dependent Gate-Level Netlist • Encrypted Black-Box • May be parameterizable • Technology Dependent Gate-Level Netlist • Layout is required • Floor-planning guidelines available • Size and Speed somewhat predictable • Layout is required • Floorplanning guidelines necessary • Size and Speed highly predictable Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Hard Core Why use Hard Cores • Encrypted Black-Box Memories Performance Not critical logic • Technology Specific Layout FPGAs and power Data paths critical logic • Size and Speed Determined • May cause routing blockages and problems Semi Reprogrammable with chip layout Custom Logic Full • Not portable to other vendors custom 2-3 X ~10 X Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet 2
Why use Hard Cores Why use Hard Cores • Implementation Level • High Performance • Microarchitecture Level • Low Power Consumption – Specialized Logic Architecture • Predictable – Application Specific Processor Core • Memories – General Purpose Processor Core • Processor Cores • Architecture Level • FPGAs – Component and Communication Selection • Analog and Mixed Signal Cores Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Examples Examples PowerPC core RAMDAC core integrated with integrated with memory IF, custom logic PLL, RAM, register file and custom logic Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Questions Communication-Based Design • Q: What is the difference between soft cores and • Separate Behavior and Interface firm cores? • Separate Core and Wrapper – A: Firm cores are secret and the systems company never get information of the internal architecture. • Q: What advantages do hard cores have? – A: High performance, low power, small, predictable • Discussion: Which type of cores will be most common in the near future? Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet 3
Communication-Based Design Refining Communication • Token Passing • Bus Transactions • Data and Handshaking Events • Also for Software (Shared Memory, Queues, Posted Events, etc.) • Between HW and SW (Interrupts, Polling) • Between SW and HW (I/O instr, registers) Refining Communication Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Example Questions • Q: What is the key characteristic of communication-based design? – A: Separating Behavior from Communication • Q: On which abstraction levels is the separation maintained? – A: On all levels of abstraction • Discussion: Why is this approach good? Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Platform-Based Design Platform-Based Design • Manufacturing Platform • Architecture Platform – Application cannot be developed entirely in isolation from architecture – Exports models and estimators to application development • System Platform Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet 4
Architecture Platform Hardware Platform • A family of microprocessors that allow reuse of software • A few such platform will dominate the market for embedded systems • Requires abstracted level to be useful • This abstracted level is called API (Application Program Interface) Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Software Platform Platform Development • RTOS • I/O subsystem • Device Drivers • Network communication subsystem • Together with hardware platform it forms the system platform Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet Power Control Power Control • Industrial Design from Magneti-Marelli • Failure detection and recovery • Engine status computation • Injection and ignition control law • Actuation drivers • Modelled in CFSM Tomas Henriksson Tomas Henriksson Computer Engineering Computer Engineering Dept. of EE Dept. of EE Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001 Linköpings universitet Linköpings universitet 5
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