Outline Introduction Core (IP)-Based Design Challenges - - PDF document

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Outline Introduction Core (IP)-Based Design Challenges - - PDF document

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Outline Introduction Core (IP)-Based Design Challenges Reusable Components Communication-Based Design Processors and Architectures for Platform-Based Design Embedded Systems Networks On-Chip Tomas Henriksson Tomas

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Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Core (IP)-Based Design

Processors and Architectures for Embedded Systems

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Outline

  • Introduction
  • Challenges
  • Reusable Components
  • Communication-Based Design
  • Platform-Based Design
  • Networks On-Chip

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Chip Overview

Several millions of transistors available A processor core needs only some hundred K gates Several processors fit on one chip

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Reuse

  • # transistors increases 60% / year
  • Design productivity increases 20% / year
  • Design gap is growing
  • Combat by reuse
  • Reuse by IPRs
  • Requires new specification, methodolgy and

tools

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Forecast

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Challenges

  • Core-based design solves all problems?
  • Maybe, but several challenges remain:

– Core description – System description – Core intercommunication – Verification – Production volume

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SLIDE 2

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Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Reusable Components

  • Intellectual Property (IP)
  • Intellectual Property Rights (IPR)
  • Synthesizable Core – Technology Independent
  • Soft Core – Technology Dependent Netlist
  • Firm Core – Technology Dependent Netlist
  • Hard Core – Fixed Layout

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Synthesizable Core

  • High-Level Description (e.g. VHDL or

Verilog)

  • Functional Verification Completed
  • Synthesis is required
  • Layout is required
  • Size and Speed not predictable

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Soft Core

  • Technology Dependent Gate-Level Netlist
  • May be parameterizable
  • Layout is required
  • Size and Speed somewhat predictable
  • Floorplanning guidelines necessary

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Firm Core

  • Encrypted Black-Box
  • Technology Dependent Gate-Level Netlist
  • Floor-planning guidelines available
  • Layout is required
  • Size and Speed highly predictable

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Hard Core

  • Encrypted Black-Box
  • Technology Specific Layout
  • Size and Speed Determined
  • May cause routing blockages and problems

with chip layout

  • Not portable to other vendors

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Why use Hard Cores

Full custom Semi Custom 2-3 X Reprogrammable Logic ~10 X Memories FPGAs Data paths Performance and power critical logic Not critical logic

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SLIDE 3

3

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Why use Hard Cores

  • Implementation Level
  • Microarchitecture Level

– Specialized Logic Architecture – Application Specific Processor Core – General Purpose Processor Core

  • Architecture Level

– Component and Communication Selection

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Why use Hard Cores

  • High Performance
  • Low Power Consumption
  • Predictable
  • Memories
  • Processor Cores
  • FPGAs
  • Analog and Mixed Signal Cores

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Examples

RAMDAC core integrated with custom logic

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Examples

PowerPC core integrated with memory IF, PLL, RAM, register file and custom logic

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Questions

  • Q: What is the difference between soft cores and

firm cores?

– A: Firm cores are secret and the systems company never get information of the internal architecture.

  • Q: What advantages do hard cores have?

– A: High performance, low power, small, predictable

  • Discussion: Which type of cores will be most

common in the near future?

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Communication-Based Design

  • Separate Behavior and Interface
  • Separate Core and Wrapper
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Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Communication-Based Design

Refining Communication

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Refining Communication

  • Token Passing
  • Bus Transactions
  • Data and Handshaking Events
  • Also for Software (Shared Memory,

Queues, Posted Events, etc.)

  • Between HW and SW (Interrupts, Polling)
  • Between SW and HW (I/O instr, registers)

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Example

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Questions

  • Q: What is the key characteristic of

communication-based design?

– A: Separating Behavior from Communication

  • Q: On which abstraction levels is the

separation maintained?

– A: On all levels of abstraction

  • Discussion: Why is this approach good?

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Platform-Based Design

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Platform-Based Design

  • Manufacturing Platform
  • Architecture Platform

– Application cannot be developed entirely in isolation from architecture – Exports models and estimators to application development

  • System Platform
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SLIDE 5

5

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Architecture Platform

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Hardware Platform

  • A family of microprocessors that allow

reuse of software

  • A few such platform will dominate the

market for embedded systems

  • Requires abstracted level to be useful
  • This abstracted level is called API

(Application Program Interface)

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Software Platform

  • RTOS
  • I/O subsystem
  • Device Drivers
  • Network communication subsystem
  • Together with hardware platform it forms

the system platform

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Platform Development

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Power Control

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Power Control

  • Industrial Design from Magneti-Marelli
  • Failure detection and recovery
  • Engine status computation
  • Injection and ignition control law
  • Actuation drivers
  • Modelled in CFSM
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SLIDE 6

6

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Protocol Stack

  • CFSM model
  • Different execution rates

– 1 kHz user interface – 8 kHz µlaw encoder – 1.2 MHz physical layer

  • 25 times less code than previous version

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Protocol Stack

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Questions

  • Q: What knowledge is needed in order to be able

to develop an architecture platform?

– A: Application domain, silicon process characteristics, evaluation models

  • Q: Which are the important parts of the software

platform?

– A: RTOS, I/O, device drivers, network comm.

  • Discussion: How many architecture platforms will

we have in a few years?

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Networks on Chip

  • Several hundreds of cores on one chip
  • Arbitration based buses are not providing

enough communication capacity

  • Parallel communication is superior
  • Network on chip is the probable solution
  • So far no commercial systems, Sonics have

micronetwork, but it is actually a bus

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Network on Chip

Network on chip Core Core Core Core Core Core Core Core

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Network on Chip

  • Protocol Layers
  • Switches/Routers
  • Synchronous/Asynchronous
  • Wrappers
  • Network Topology
  • Routing Algorithms
  • Layout
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SLIDE 7

7

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Protocol Layers

Physical Data Link Network Transport Session Presentation Application Needed

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Switches/Routers

Control N Packet forwarding Control communication Point-to-point links Buffer size?

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Synchronous/Asynchronous

  • Globally Asynchronous Locally

Synchronous

  • Not always true, synchronous networks on

chip exist

  • Wrapper handles synchronization

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Wrappers

  • Synchronization
  • Width adaptation
  • Bitrate adaptation
  • Error control?

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Network Topology

  • Connectivity
  • Latency depends on number of hops
  • Publications:

– 4 links/switch one in each direction, core on the edge – 5 links/switch one in each direction + one core – 6 links/switch as a honeycomb structure

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Routing Algorithms

  • Static vs. Dynamic
  • Central vs. Distributed
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SLIDE 8

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Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Layout

  • Performance dependent on layout
  • Maximum distance important
  • New floorplanning tools are needed
  • Gives control of all long wires

Core (IP)-Based Design – Lecture 5&6 in Hardware/Software Co-Design 2001

Tomas Henriksson Computer Engineering

  • Dept. of EE

Linköpings universitet

Questions

?