[PPT] - NAVIGATING BIG DATA with High-Throughput, Energy- Efficient Data PowerPoint Presentation

SLIDE 1

NAVIGATING BIG DATA

with High-Throughput, Energy- Efficient Data Partitioning

Lisa Wu, R.J. Barker, Martha Kim, and Ken Ross Columbia University

1 Sunday, July 28, 2013

SLIDE 2

BIG DATA is here

Sources: IDC Worldwide Big Data Technology and Services 2012-2015 Forecast, #233485, March 2012 The Next Web, DAZEINFO NetApp

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SLIDE 3

Do sunblock sales correlate with weather?

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SLIDE 4

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JOINs = Cross Reference

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SLIDE 5

SALES WEATHER

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JOINs = Cross Reference

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SLIDE 6

SALES WEATHER

JOINDATE

4

JOINs = Cross Reference

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SLIDE 7

SALES WEATHER JOINDATE(SALES, WEATHER)

JOINDATE

4

JOINs = Cross Reference

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SLIDE 8

0% 25% 50% 75% 100% 17 9 11 5 7 8 22 1 2 12 21 18 19 10 15 3 20 4 16 14 13 6 Avg.

Runtime in Join TPC-H Query

JOINs = 47% TPC-H Execution Time

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SLIDE 9

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Naïve JOINs of BIG DATA Thrash the Cache

SALES WEATHER

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SLIDE 10

Scan

6

Naïve JOINs of BIG DATA Thrash the Cache

SALES WEATHER

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SLIDE 11

Scan Random Lookup

6

Naïve JOINs of BIG DATA Thrash the Cache

SALES WEATHER

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SLIDE 12

Scan Random Lookup Small table doesn’ t fit into cache ➛ lookups thrash

6

Naïve JOINs of BIG DATA Thrash the Cache

SALES WEATHER

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SLIDE 13

Partitioned JOIN

SALES WEATHER 7 Columbia University

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SLIDE 14

Partitioned JOIN

SALES WEATHER SALES_0 SALES_1 SALES_2 SALES_3 7 Columbia University

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SLIDE 15

Partitioned JOIN

SALES WEATHER SALES_0 SALES_1 SALES_2 WEATHER_1 WEATHER_2 WEATHER_3 SALES_3 7 WEATHER_0 Columbia University

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SLIDE 16

Partitioned JOIN

SALES WEATHER SALES_0 SALES_1 SALES_2 WEATHER_1 WEATHER_2 WEATHER_3 SALES_3 7 WEATHER_0

DATE SALES_0 WEATHER_0

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SLIDE 17

Partitioned JOIN

SALES WEATHER SALES_0 SALES_1 SALES_2 WEATHER_1 WEATHER_2 WEATHER_3 SALES_3

DATE SALES_1 WEATHER_1 DATE SALES_2 WEATHER_2 DATE SALES_3 WEATHER_3

7 WEATHER_0

DATE SALES_0 WEATHER_0

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SLIDE 18

JOIN Runtime

time Naive Join Partitioned Join

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SLIDE 19

JOIN Runtime

time Naive Join Partitioned Join

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SLIDE 20

JOIN Runtime

time Naive Join Partitioned Join Partition SALES Partition WEATHER

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SLIDE 21

JOIN Runtime

time Naive Join Partitioned Join Partition SALES Partition WEATHER 1 2 3

Join

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SLIDE 22

JOIN Runtime

time Naive Join Partitioned Join Partition SALES Partition WEATHER 1 2 3

Join

8

Partition ≈ 50% of State-of-the-Art Joins

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SLIDE 23

JOIN Runtime

time Naive Join Partitioned Join Partition SALES Partition WEATHER 1 2 3

Join

8

Partition ≈ 50% of State-of-the-Art Joins

Aggregate

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SLIDE 24

JOIN Runtime

time Naive Join Partitioned Join Partition SALES Partition WEATHER 1 2 3

Join

8

Partition ≈ 50% of State-of-the-Art Joins

Aggregate Sort

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SLIDE 25

9

Data Partitioning is...

Columbia University

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SLIDE 26

broadly applicable in the database domain
partitioned-operations reduce I/O cost,

increase parallel processing, and reduce shipping costs

9

Data Partitioning is...

Columbia University

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SLIDE 27

broadly applicable in the database domain
partitioned-operations reduce I/O cost,

increase parallel processing, and reduce shipping costs

widely used by commercial databases
Oracle 11g, IBM DB2, Microsoft SQL Server

9

Data Partitioning is...

Columbia University

9 Sunday, July 28, 2013

SLIDE 28

broadly applicable in the database domain
partitioned-operations reduce I/O cost,

increase parallel processing, and reduce shipping costs

widely used by commercial databases
Oracle 11g, IBM DB2, Microsoft SQL Server
applicable in the non-database domain
divide-and-conquer, map-reduce

9

Data Partitioning is...

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SLIDE 29

7.5 15 22.5 30 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

SW Partitioning Performance

1 thread 16 threads Potential System Memory Throughput

10

25.6 GB/s

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SLIDE 30

7.5 15 22.5 30 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

SW Partitioning Performance

1 thread 16 threads Potential System Memory Throughput

10

25.6 GB/s 3 GB/s

Columbia University

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SLIDE 31

Research Overview

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

11

New Modules

Columbia University

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SLIDE 32

Research Overview

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

11

New Modules

Hardware accelerated range partitioner (HARP): 7.8X more performance @ 7.5X less energy

Columbia University

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SLIDE 33

Research Overview

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

11

New Modules

Streaming framework: Can keep up with the throughput of HARP Hardware accelerated range partitioner (HARP): 7.8X more performance @ 7.5X less energy

Columbia University

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SLIDE 34

Remainder of the Talk

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

12

New Modules

Brief System Overview
HARP UArch
Streaming Framework

UArch

HARP and Streaming

Framework Evaluation

Discussion

Columbia University

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SLIDE 35

HARP System Architecture

13

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

Columbia University

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SLIDE 36

HARP System Architecture

13

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

HARP communicates to/from memory through stream buffers: SBin, SBout

Columbia University

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SLIDE 37

HARP System Architecture

13

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

HW Partitioning with SW configuration HARP communicates to/from memory through stream buffers: SBin, SBout

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SLIDE 38

Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

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SLIDE 39

Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

RDs WRs

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SLIDE 40

Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly

RDs WRs

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SLIDE 41

Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly

CMP , BR, etc. RDs WRs

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SLIDE 42

LDs STs Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly

CMP , BR, etc. RDs WRs

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SLIDE 43

LDs STs Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly

CMP , BR, etc. RDs WRs

Executed on unmodified hardware

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SLIDE 44

LDs STs Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly Modified SW in Assembly

CMP , BR, etc. RDs WRs

Executed on unmodified hardware

Columbia University

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SLIDE 45

LDs STs Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly Modified SW in Assembly

CMP , BR, etc.

Hardware Accelerated

RDs WRs

Executed on unmodified hardware Executed

n HARP

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SLIDE 46

SBLDs SBSTs LDs STs Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly Modified SW in Assembly SB Insts SB Insts

CMP , BR, etc.

Hardware Accelerated

RDs WRs

Executed on unmodified hardware Executed

n HARP

Columbia University

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SLIDE 47

SBLDs SBSTs LDs STs Table Partition Lock Acq. Lock Rel.

Original SW

Programming Model

14

Original SW in Assembly Modified SW in Assembly SB Insts SB Insts

ASM ASM ASM ASM CMP , BR, etc.

Hardware Accelerated

RDs WRs

Executed on unmodified hardware Executed

n HARP

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SLIDE 48

X Y Z 15 8 27 20 52 29 16 31

Range Partition

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SLIDE 49

X Y Z 15 8 27 20 52 29 16 31

Range Partition

key

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SLIDE 50

X Y Z 15 8 27 20 52 29 16 31

Range Partition

key

10 20 30

splitters

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SLIDE 51

X Y Z 15 8 27 20 52 29 16 31

Range Partition

key

10 20 30

splitters

8

partitions

<= >

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SLIDE 52

X Y Z 15 8 27 20 52 29 16 31

Range Partition

key

10 20 30

splitters

8

partitions

<= >

15 20 16 27 29 52 31

<= <= > >

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SLIDE 53

From SBin

To SBout

HARP Microarchitecture

16

HARP ISA set_splitter partition_start partition_stop

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SLIDE 54

From SBin

To SBout

HARP Microarchitecture

16

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

HARP ISA set_splitter partition_start partition_stop

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SLIDE 55

Step 1: HARP Configuration

17

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

HARP ISA partition_start partition_stop set_splitter

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SLIDE 56

Step 1: HARP Configuration

17

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

10 20 30 HARP ISA set_splitter partition_start partition_stop

Columbia University

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SLIDE 57

Step 2: Signal HARP to Start Processing

18

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

10 20 30 HARP ISA partition_stop set_splitter partition_start

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SLIDE 58

Step 2: Signal HARP to Start Processing

18

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

10 20 30 HARP ISA partition_start partition_stop set_splitter

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SLIDE 59

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 3: Serialize SBin Cachelines into Records

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10 20 30 HARP ISA set_splitter partition_start partition_stop

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SLIDE 60

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 3: Serialize SBin Cachelines into Records

19

10 20 30 HARP ISA set_splitter partition_start partition_stop

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SLIDE 61

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 4: Comparator Conveyor

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10 20 30 HARP ISA set_splitter partition_start partition_stop

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SLIDE 62

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 4: Comparator Conveyor

15 15 15, part2

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10 20 30 HARP ISA set_splitter partition_start partition_stop

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SLIDE 63

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 5: Merge Output Records to SBout

21

10 20 30 HARP ISA set_splitter partition_start partition_stop

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SLIDE 64

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 5: Merge Output Records to SBout

21

10 20 30 HARP ISA set_splitter partition_start partition_stop

Columbia University

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SLIDE 65

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 6: Drain In-Flight Records and Signal HARP to Stop Processing

22

10 20 30 HARP ISA set_splitter partition_start partition_stop

Columbia University

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SLIDE 66

From SBin

To SBout

< = < = < =

Serializer

1

Conveyor

2

Merge

3 WE WE WE WE

Step 6: Drain In-Flight Records and Signal HARP to Stop Processing

22

10 20 30 HARP ISA set_splitter partition_start partition_stop

Columbia University

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SLIDE 67

Streaming Framework Architecture

23

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

Inspired by Jouppi’s work

Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In ISCA, 1990.

Columbia University

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SLIDE 68

Streaming Framework Architecture

23

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

Software- controlled data streaming in/out

Inspired by Jouppi’s work

Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In ISCA, 1990.

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SLIDE 69

Step 1: Issue sbload from Core

24

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

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SLIDE 70

Step 1: Issue sbload from Core

24

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbstore sbsave sbrestore sbload

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SLIDE 71

Step 2: Send sbload from Req Buffer to Memory

25

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

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SLIDE 72

Step 2: Send sbload from Req Buffer to Memory

25

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

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SLIDE 73

Step 2: Send sbload from Req Buffer to Memory

25

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

C: Cache S: SB

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SLIDE 74

Step 3: Data Return from Memory to SBin

26

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

C: Cache S: SB

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SLIDE 75

Step 3: Data Return from Memory to SBin

26

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

C: Cache S: SB

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SLIDE 76

Step 3: Data Return from Memory to SBin

26

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

C: Cache S: SB

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SLIDE 77

Step 4: HARP Pulls Data from SBin and Pushes Data to SBout

27

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

C: Cache S: SB

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SLIDE 78

Step 4: HARP Pulls Data from SBin and Pushes Data to SBout

27

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

✗ ✗ ✗

C: Cache S: SB

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SLIDE 79

Step 5: Issue sbstore from Core

28

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

Columbia University

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SLIDE 80

Step 5: Issue sbstore from Core

28

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbsave sbrestore sbstore

Columbia University

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SLIDE 81

Step 6: Data Copied from head of SBout to Store Buffer

29

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

Columbia University

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SLIDE 82

Step 6: Data Copied from head of SBout to Store Buffer

29

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

Columbia University

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SLIDE 83

Step 7: Data Written Back to Memory via Existing Store Datapath

30

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

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SLIDE 84

Step 7: Data Written Back to Memory via Existing Store Datapath

30

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

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SLIDE 85

Interrupts and Context Switches

31

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

Columbia University

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SLIDE 86

Interrupts and Context Switches

31

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbsave sbrestore

Architectural

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SLIDE 87

Interrupts and Context Switches

31

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore sbrestore

Architectural

sbsave

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SLIDE 88

Interrupts and Context Switches

31

Memory Core

L1

L2 SBin LLC

HARP

SBout

Req Buffer Store Buffer

SB ISA sbload sbstore

Architectural

sbsave sbrestore

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SLIDE 89

Accelerator Integration Choice

Tightly coupled and software controlled:
area/power savings
coherence
utilize hardware prefetchers
software-managed data layout
address-free domain for accelerators

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SLIDE 90

Remainder of the Talk

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

33

Brief System Overview
HARP UArch
Streaming Framework

UArch

HARP and Streaming

Framework Evaluation

Discussion and DSE

Columbia University

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SLIDE 91

Evaluation Methodology

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SLIDE 92

Evaluation Methodology

HARP
Bluespec System Verilog implementation
Cycle-accurate simulation in BlueSim
Synthesis, P&R with Synopsys (32nm std cells)

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SLIDE 93

Evaluation Methodology

HARP
Bluespec System Verilog implementation
Cycle-accurate simulation in BlueSim
Synthesis, P&R with Synopsys (32nm std cells)
Streaming framework
3 versions of 1GB table memcpy: c-lib, ASM

(scalar), ASM(vector)

Conservative area/power estimates with CACTI

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SLIDE 94

Area and Power Overheads

0% 4% 8% 11% 15% 15 31 63 127 255 511

Area (% Xeon core) HARP Stream Buffers Number of Partitions

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SLIDE 95

Area and Power Overheads

0% 4% 8% 11% 15% 15 31 63 127 255 511

Area (% Xeon core) HARP Stream Buffers

0% 2% 4% 6% 8% 10% 15 31 63 127 255 511

Power (% Xeon core) Number of Partitions

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SLIDE 96

SW Partitioning Performance

36 2 4 6 8 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions 1 thread 16 threads

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SLIDE 97

2 4 6 8 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

Performance Evaluation

1 thread 16 threads 1 thread + HARP

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SLIDE 98

2 4 6 8 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

Performance Evaluation

1 thread 16 threads 1 thread + HARP

37

7 .8x

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SLIDE 99

2 4 6 8 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

Performance Evaluation

1 thread 16 threads 1 thread + HARP

37

7 .8x 8.8x

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SLIDE 100

Streaming Framework Provides Sufficient BW to Feed HARP?

38 1.75 3.5 5.25 7 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions 1 thread + HARP

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SLIDE 101

Streaming Framework Provides Sufficient BW to Feed HARP?

38 1.75 3.5 5.25 7 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

Our measure- ments scalar ASM vector ASM memcpy

1 thread + HARP

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SLIDE 102

Streaming Framework Provides Sufficient BW to Feed HARP?

38 1.75 3.5 5.25 7 150 300 450 600

Partitioning Throughput (GB/s) Number of Partitions

vector ASM memcpy From the literature Our measure- ments scalar ASM vector ASM memcpy

1 thread + HARP

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SLIDE 103

HARP Energy vs. SW

5 10 15 20 150 300 450 600

Partitioning Energy (J/GB) Number of Partitions 1 thread 16 threads 1 thread + HARP

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SLIDE 104

HARP Energy vs. SW

5 10 15 20 150 300 450 600

Partitioning Energy (J/GB) Number of Partitions 1 thread 16 threads 1 thread + HARP

6.3x

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SLIDE 105

HARP Energy vs. SW

5 10 15 20 150 300 450 600

Partitioning Energy (J/GB) Number of Partitions 1 thread 16 threads 1 thread + HARP

6.3x 7 .3x

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SLIDE 106

Remainder of the Talk

SBin SBout

HARP Core L1

Memory Controller Memory

SBin SBout

HARP Core L1 L2 L2

40

Brief System Overview
HARP UArch
Streaming Framework

UArch

HARP and Streaming

Framework Evaluation

Discussion

Columbia University

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SLIDE 107

255 -way partitioning 4B keys 16B records

Design Space Exploration (in the paper)

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SLIDE 108

255 -way partitioning 4B keys 16B records

Design Space Exploration (in the paper)

41

255 511 127 63 31 15

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SLIDE 109

255 -way partitioning 4B keys 16B records

Design Space Exploration (in the paper)

41

255 511 127 63 31 15 16B 8B 4B

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SLIDE 110

255 -way partitioning 4B keys 16B records

Design Space Exploration (in the paper)

41

255 511 127 63 31 15 16B 8B 4B 8 B 1 6 B 4 B

Columbia University

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SLIDE 111

Coping with Fixed Resources: Partitioning Factor > Partitioner Size

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SLIDE 112

Coping with Fixed Resources: Partitioning Factor > Partitioner Size

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HARP

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SLIDE 113

Coping with Fixed Resources: Partitioning Factor > Partitioner Size

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HARP HARP

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SLIDE 114

Coping with Fixed Resources: Record Width > Record Size

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SLIDE 115

Coping with Fixed Resources: Record Width > Record Size

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Coping with Fixed Resources: Record Width > Record Size

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HARP HARP

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SLIDE 117

Conclusion

Data partitioning, which does not appear

compute-heavy, can still benefit from acceleration

Microarchitecture to pair streaming accelerator(s)

to work closely with CPU

Demonstrate how accelerators can rebalance

system and improve memory bandwidth utilization, a scarce resource in big data analytics

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FIN

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