Logical and Physical Restructuring of Fan-in Trees Hua Xiang Haoxing Ren Louise Trevillyan Lakshmi Reddy + Ruchir Puri Minsik Cho I BM T.J. Watson Research Center + I BM EDA Lab. STG
Introduction As feature sizes shrink and design complexity increases, the use of integrated logic synthesis and physical design is expanding. Tree restructure for SFFT (Symmetric-Function Fan-in Tree) Trees are created during logic synthesis without placement information Tree placement may be far from optimal since tree structure is fixed during physical design Tree restructure can produce a more placeable and wire-efficient design.
Symmetric-Function Fan-in Tree (SFFT) A symmetric-function fan-in tree is a fanout-free logic cone Compute a symmetric function All of the leaf nets in its support set are commutative The tree can be implemented with various structures of a uniform set of gates (i.e., AND, OR, XOR) a a a b b b AND AND AND c c c Ga Ga Ga AND AND Gd Gd e e e AND AND AND AND AND AND f f f Gb Gb Gb Gn Gn Gn g g g h h h AND AND AND l Gc l Gc l Gc F=a·b·c·e·f·g·h·l SFFT trees are frequently found in designs, especially when the design originated as two-level logic Rebuild SFFT trees based on the placement information to reduce wire length
Tree Restructure Algorithm outline SFFT_Restructure ( TreeRoot , Threshold ) 1. Identify SFFT tree with root TreeRoot 2. Get the locations of all leaf pins and root pin 3. If # leaf pins < Threshold 4. Apply Dynamic programming based algorithm 5. else 6. Apply Steiner-Tree based restructure algorithm 7. Output the new SFFT tree
AND SFFTs Possible gates in AND SFFTs Any gates whose logic can be expressed by AND/NOT operations Gate Type Function NAND G1 AND F = a·b a NOR G2 NAND F = a·b INV G4 NAND OR F = a·b G3 b AND NOR G6 F = a·b AND G5 e f NOT c d F = a BUF F = a F = a·b·c·d·e·f
Stack-based Tree Identification Build look-up table to convert NAND NAND NAND NAND NAND NAND NAND NAND gates to AND/NOT gates and and and and and and and G1 G1 G1 G1 G1 G1 G1 G1 b b b b b b b b not Build the initial stack based on a a a a a a a a and not not not not not NOR NOR NOR NOR NOR NOR NOR NOR the tree root Latch Latch Latch Latch Latch Latch Latch G2 G2 G2 G2 G2 G2 G2 G2 and and and and and and G9 G9 G9 G9 G9 G9 G9 . . . . . . . . . . . . . . . . . . . . . d d d d d d d d c c c c c c c c Traverse from top to bottom to and INV INV INV INV INV INV INV INV . . . . . . . and G4 G4 G4 G4 G4 G4 G4 G4 NAND NAND NAND NAND NAND NAND NAND NAND not . . . . . . . identify tree nodes and and G3 G3 G3 G3 G3 G3 G3 G3 g g g g g g g g and not f f f f f f f f e e e e e e e e . . . . . . . and and Traverse stops AND AND AND AND AND AND AND AND . . . . . . . and G6 G6 G6 G6 G6 G6 G6 G6 AND AND AND AND AND AND AND AND k . k . k . k . k . k . k . . . . . . . . and j j j j j j j j G5 G5 G5 G5 G5 G5 G5 G5 Multiple-pin net k i i i i i i i i h h h h h h h h and and Infeasible gates OR OR OR OR OR OR OR NAND NAND NAND NAND NAND NAND NAND not not G7 G7 G7 G7 G7 G7 G7 G8 G8 G8 G8 G8 G8 G8 and and Invalid logic
Tree Restructure Rebuild SFFT trees for shorter wire length Keep the leaf input nets and root output net unchanged Remove all internal gates/nets Use AND/NOT gates to rebuild the tree Restructure algorithms Dynamic programming based restructure Optimal solution for a given tree Long runtime Steiner-Tree based restructure The new tree follows the shape of a Steiner Tree for shorter wire length Build sub-trees with DP based tree restructure Balance quality and runtime
DP based Tree Restructure T1 T1 T1 {T1} SFFT_DP ( TreeRoot ) {T2} {S1} S1 S1 S1 T2 T2 T2 1. Build connectivity graph 2. Let each leaf/Steiner node be a tree, R R R T4 T4 T4 {R} and push them to Queue {T4} 3. While (! Queue .empty) { {S2} S2 S2 S2 4. subtree = Queue .pop_front T3 T3 T3 {T3} 5. for parent node P of subtree . TreeRoot (1) (2) (3) 6. merge trees related to P with subtree T1 T1 T1 7. prune redundant trees {{S1},{S1 T1}, {T1} {S1 T2}, 8. push the new trees in Queue T1 {{S1},{S1 T1}} {S1 T2}} 9. } S1 S1 S1 T2 T2 10. Return a tree at TreeRoot with R R R T4 T4 max leaf set and min wire length {{R},{R T1}} {{S2},{S2 T1}} S2 S2 S2 T3 T3 (4) (5) (6)
Steiner Tree based Restructure T4 T4 T4 T4 (6, 1) (6, 1) T1 T1 T1 T1 (5, 1) (5, 1) S3 S3 S3 T5 T5 (5, 2) T5 (5, 2) T5 (6, 1) (6, 1) (5, 1) (4, 3) (3, 8) (5, 1) (3, 8) S4 S4 (4, 3) S4 T6 T6 T6 T6 T2 S1 (4, 5) S1 (4, 5) S2 S2 (5, 1) S2 (5, 1) T2 T2 T2 T7 T7 T7 T7 (5, 2) (5, 2) S5 S5 (6, 1) S5 (6, 1) (5, 1) (5, 1) T3 T3 T3 T3 (6, 1) (6, 1) T8 T8 T8 T8 S6 S6 S6 (3, 1) (3, 1) (2, 9) (2, 9) T9 T9 T9 T9 (2, 1) (2, 1) (1, 10) (1, 10) T10 T10 T10 T10 S7 S7 S7 (1, 1) (1, 1) (level, children) (level, children) T11 T11 T11 (0, 11) T11 (0, 11) root root root root (1) (2) (3) (4) T4 T4 T4 T4 T1 T1 T1 T1 (5, 1) (5, 1) T5 T5 T5 T5 (3, 4) (3, 1) (3, 1) (5, 1) (4, 3) (3, 4) (5, 1) (4, 3) S4 S4 S4 S4 T6 T6 T6 T6 (4, 1) S1 (4, 1) S1 T2 T2 S2 S2 S2 S2 T2 T2 T7 T7 T7 T7 S5 S5 S5 S5 (5, 1) (5, 1) T3 T3 T3 T3 T8 T8 T8 T8 S6 (3, 1) S6 (3, 1) S6 (3, 1) (2, 5) (2, 5) (2, 2) T9 T9 T9 T9 (2, 1) (2, 1) (2, 1) (1, 6) (1, 6) T10 (1, 3) T10 T10 T10 S7 S7 S7 (1, 1) (1, 1) (1, 1) (level, children) (level, children) (level, children) (level, children) T11 root(0, 7) T11 root(0, 7) T11 root(0, 4) T11 root (5) (6) (7) (8)
Experimental Results Algorithms were implemented in C, and have been integrated into a physical-synthesis system Tested on linux workstations (2.6GHz) Test cases were derived from industrial designs
Experimental Results (cont) Restructuring Results with Re-placement STWL: Total wire length of SFFT trees TWL: Total wire length AEC: Average edge congestions ANC: Average net congestions AEC20: AEC20: Average Edge Congestions of top 20% congested edges ANC20: AEC20: Average Net Congestions of top 20% congested nets Number of nets whose congestion ≥ 90% Net90: Number of nets whose congestion ≥ 100% Net100:
Experimental Results (cont) Restructuring Results with Legalization STWL: Total wire length of SFFT trees TWL: Total wire length AEC: Average edge congestions ANC: Average net congestions AEC20: AEC20: Average Edge Congestions of top 20% congested edges ANC20: AEC20: Average Net Congestions of top 20% congested nets Number of nets whose congestion ≥ 90% Net90: Number of nets whose congestion ≥ 100% Net100:
Experimental Results (cont) (a) Original Tree (b) Steiner Tree (c) Restructured Tree (d) Legalized Tree Wire length: 1594 Wire Length: 2719 Wire Length: 2523 Wire Length: 5627
Conclusion SFFT tree is a fanout-free cone of logic that computes a symmetric function, so that all of the leaf nets in its support set are commutative. Propose efficient algorithms to identify SFFT trees and restructure them. SFFT tree restructure helps to get better tree shapes, reduce wire length and congestion on some designs.
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