FT-UNSHADES2. H.G. Miranda, M.A. Aguirre, J. Barrientos, L. Sanz - PowerPoint PPT Presentation

FT-UNSHADES2. H.G. Miranda, M.A. Aguirre, J. Barrientos, L. Sanz Electronic Engineering Dpt. School of Engineering. University of Sevilla (SPAIN) Sevilla, March 2014

FT -UNSHADES goals  FT -UNSHADES is a tool for SEE EMULATION, at netlist level.  Emulation is the use of programmable hardware structures to perturb the design under test.  It is a highly flexible and simple solution from the designer point of view.  The goal is to perform the injections in a deterministic manner.  Combines Massive Injections with cycle accurate analysis, in the same tool  Exploits the mechanisms of Xilinx FPGA, named Partial Reconfiguration, Snapshot and Readback Other features:  Remote access  Internal analysis  Test in the beam  Targeting FPGAs for analysis

What for, FTU2? 1. Check the protection level 2. Hierarchical assessment of the submodules 3. Check protections 4. Selective redundancies 5. Reset and initialization policy 6. Digital SETs 7. MBU studies 8. SEE detailed analysis

FT-UNSHADES2 in a ASIC mode  FTU2 is a contract with ESA: “ High Capacity, High Speed IC Test System for Automatic Fault Injection and Analysis (FT-UNSHADES 2 )”  FTU2 is a platform designed to assess the reliability of a netlist at design level.  The processing is determined knowing a priori where, when and how to inject the faults over USER REGISTERS.  In FTU2 both sights are implemented: fault campaigns and single fault detailed analysis  Several SEEs models are implemented: SEU and MBU, and under certain conditions, SETs.  The design flow has been is reduced to a FPGA standard implementation and a simulation.  The PARTIAL RECONFIGURATION feature of Xilinx FPGAs is exploited to generate bit- flips into the USER REGISTERS, LUTs, BRAMs…

FTU2 in FPGA mode Originally FTU was thought trough the assessment of ASIC netlist. FTU2 has been extended to inject on SRAM-FPGAs configuration. • The basic mechanism to inject over the FPGA CONFIGURATION is the same than USER REGISTERS. • It is not constrained to a specific FPGA • Analyzes in detail the propagation of a fault in the configuration, and the possible corruption of the user logic. • The study of techniques for scrubbing policy

FT -UNSHADES2 in a nutshell: the structure of the hardware Target FPGA I / Os Two twin • Bitstream FPGAs • Injection Batch Control • Workload hosts two FPGA M copies of A SELECTMAP R D the netlist. The design runs along in parallel Target FPGA I / Os

FT -UNSHADES2 in a nutshell: the structure of the hardware Target DRAM Service FPGA Memory FPGA Control FPGA

FT -UNSHADES2 in a nutshell: the design preparation flow Workload Workload High Level Description High Level Description High Level Simulation High Level Simulation • Bitstream (.bit) • Bit allocation file (.ll) Realiability Constraints Synthesis Constraints Synthesis Assessment • Port location (.pin) FPGA • Workload VCD stimuli (*.vcd) Workload Technology For FPGA flow Technology Technology Level Technology Level Place & Route Place & Route • Simulation Simulation Configuration allocation (*.cl) Realiability FPGA description ASIC prototype Assessment 1. Fit your design in the target FPGA 2. Allocate I/Os 3. Simulate and extract inputs 4. Finish the standard flow

LOCAL COMPUTER FTUNSHADES SERVER Design.pin Make User Design.pin Design.ucf ConstraintsFile Design (HDL) Simulation ISE Make stimuli Design.dat Design.vcd file Xilinx Design.bit Design.bit Synthesis Design.ll & Design.ll PAR FTU2 files

THE HARDWARE….

FTU2: Physical Layer  FTU2 is built from a MB and 2 DBs: ◦ The MB is a Xilinx ML510 PCI socket for USB interface with the server PCIE sockets for the DBs Control FPGA (XC5VFX130T) DDR2 sockets for DIMM modules (512MB)

FTU2: Physical Layer  FTU2 is built from a MB and 2 DBs: ◦ The design of the DB is original ATX power connector PCIE x16 card edge Target FPGA V5 FF1136 Package Service FPGA (XC5VFX70T)

FTU2: Physical Layer  FTU2 is built from a MB and 2 DBs: ◦ The design of the DB is original Virtex5 FF1136 package:  XC5VLX50T  XC5VLX85T  XC5VLX110T  XC5VLX155T  XC5VSX50T  XC5VSX95T  XC5VFX70T  XC5VFX100T

FTU2: Physical Layer  FTU2 is linked to the uff-tnt server via USB: ◦ FTDI FT2232HQ minimodule: ◦ Configured as USB to FIFO ◦ Two interfaces available ◦ USB2.0

FTU2: Physical Layer  The system is assembled into an ATX tower Motherboard GOLD Daughterboard SEU Daughterboard USB-PCI board holding the 2232H minimodule

THE FIMWARE AND THE SOFTWARE…

FT-Unshades2 Firmware  Functionality has been divided between all five FPGAs:  Control FPGA: Experiment control, communications with PC  “Gold” Service-FPGA: Feed stimuli, sample responses  “ Seu ” Service-FPGA: Feed stimuli, sample responses, Inject Faults  “Gold” Target -FPGA: 100% User design!  “ Seu ” Target -FPGA: 100% User design!

FT-Unshades2 Firmware

FT-Unshades2 Firmware  Interesting features:  PCIexpress physical layer ◦ Serialize stimuli and responses. Allow up to 512 I/Os for the Target FPGA. ◦ Each PCIe endpoint allows up to 2 Gbps of user data (full duplex)  Embedded bit-flip injector ◦ Main bottleneck in FTU1 was in the partial reconfiguration procedure used to inject the faults: frames had to travel to the PC to be modified and back again to the board  DDR2 Memory controller: ◦ Up to 512 MB for bitstream + stimuli + batch commands

FT-Unshades2 FW: Lessons Learned  Embedded bitstream manipulation module solves bottleneck detected in previous version (FTU1)  Manipulating stimuli and responses with the PPC creates a new bottleneck ◦ PPC is great for prototyping, but sub-optimal for speed ◦ Bottleneck emerges with large number of test vectors  Good news: This can be solved without modifying the hardware, only with firmware updates ◦ 1st step: Comparison module: increase speed if using compressed stimuli ◦ 2nd step: Vector feeder: increase speed by skipping PPC when reading from DDR2

FT-Unshades2 Software  Solves complexity and presents an User Friendly Framework

FTU2 in numbers 1. Fault rate achieved: 10.000 faults/sec (this figure will be improved in new versions) 2. 512 I/Os, the capacity depends on the model of the target device. 3. Current configurations Virtex 5, LX50T and FX70T (FF1136 package)

FTU2 future actions 1. Improve the fault rate 2. Continue the development of FTU2-UFF 3. Construct a “farm” of devices, support the system 4. Work with the “microprocessor mode” 5. Extend the system to a test fixture for beam testing and diagnose 6. Go ahead with the FPGA mode

Access to FTU2 For Academia:  Access is available to public academia for research purposes via internet.  An agreement between the third institution and the USE  User/Password is given  Also support beta users coordinated by ESA For industrial customers:  An agreement with UoS  Training and support  Install the FTU2 in their headquarter intranet  Sell the system and support

Thank you for your attention Q &A Contacts: aguirre@gie.esi.us.es hipolito@gie.esi.us.es david.merodio.codinachs@esa.int