Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors Radu Teodorescu Department of Computer Science and Engineering The Ohio State University http://arch.cse.ohio-state.edu T computer architecture research lab � � � � � � � � � � � � � � � � � � � � � � � � � � � � ������������������������ � � � � � � � � � � � � � � � � � � � � � � �
The case for energy efficiency T � � � � � � � � � � � � � � � � � � � � � � � � � � � � ������������������������ � � � � Energy efficiency is now crucial to all computing markets, � � � especially in the growth areas: mobile and cloud computing . � � � � � � � � � � � � � � � � computer 2 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Near-threshold voltage (NTV) T V th NT Nominal � � � V dd � V dd � � � � � � � � � � � � � 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 � � � Voltage � � � � � � � Near-threshold computing, a promising energy-efficient solution. � ������������������������ � � � � � � � � � � � � Frequency cost Energy reduction � Power reduction � � � � � � � � � � 10X 10X 100X computer 3 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Intel NTV prototype T � � � � � � � � � � � � � � � � � � � � � � � � � � � � ������������������������ � � � � � � � � � � � � � � � � � � � � � � � computer 4 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
NTV faces significant challenges T Process Voltage Reliability � � Variation Variation � � � � � � � � NTV Voltage 5% error rate � � � Emergency � � � � Probability of SRAM Bit Failure 1E+00 � � � nominal 1E-02 � � � � 1E-04 � � 1E-06 � NTV% � 1E-08 Intel Vcc-min ������������������������ � � 1E-10 0 0.5 1 1.5 2 � 900 825 750 675 600 525 450 375 300 Frequency Distribution � � Supply Voltage - millivolts � � � � � � � � � � � � � � � � � � computer 5 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Outline of our solutions T Process Voltage Reliability � � Variation Variation � � � � � � � Parichute Booster VRSync � [micro2010] [hpca2012] [isca2012] � � � � � � � � � � � � � Cores in Barrier � Power (Watts) 70 � 32 60 � Parity � Cores in Barrier Data Power (Watts) 50 24 40 � 16 30 ������������������������ 20 � � 8 10 � 0 0 Parity 36 38 40 42 44 46 48 50 � � Time (milliseconds) � � � � Voltage Speculation in Itanium II [isca2013] � � � � � � � � � � � � � � computer 6 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Outline of our solutions T Process Voltage Reliability � � Variation Variation � � � � � � � Parichute Booster VRSync � [micro2010] [hpca2012] [isca2012] � � � � � � � � � � � � � Cores in Barrier � Power (Watts) 70 � 32 60 � Parity � Cores in Barrier Data Power (Watts) 50 24 40 � 16 30 ������������������������ 20 � � 8 10 � 0 0 Parity 36 38 40 42 44 46 48 50 � � Time (milliseconds) � � � � Voltage Speculation in Itanium II [isca2013] � � � � � � � � � � � � � � computer 7 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
SRAM failure rates T 350mV 1-5% 1E+00 Probability of Bit Cell Failure � � � � � � � 1E-02 � Parichute � � 1E-04 � � � � � � � � � � � � � 1E-06 � � � � � ������������������������ � � 1E-08 � � � Intel Vcc-min � � � � � � � � 1E-10 � � � � � � � � � � 900 825 750 675 600 525 450 375 300 Supply Voltage - millivolts computer 8 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Turbo product codes T � � � � � � � � � � Parity � � � � � � Data � � � � � � � � � � � � ������������������������ � � � � � � � � � � � � � � � � � � � � � � � Parity computer 9 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Parichute ECC T 0 56 100 � Permutation 0 351 � � 437 � 511 � � � � � � 351 437 0 � � Permutation 1 100 � � 511 � � � 56 � � � � � � 87 � � � � 2 5 � 56 Permutation 2 511 204 ������������������������ � � � � � � � � � � � 201 � � 499 � � � � 73 351 � � � � � � Permutation 3 1 511 computer 10 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Parichute cache architecture T � � � � Cache � Encoder � � � � � Data Block (cache line) Data In Data Parity + Data bits Redundant bits Permutation Network � � � Permutation 0 Permutation 1 Permutation N � � � � Parity Parity Parity � encoders encoders encoders � � PW PW PW ... PW PW PW ... ... PW PW PW ... � � � � Parity Group 0 Parity Group 1 Parity Group N � � � � Line 0 ������������������������ � � � Line 1 � Decoder � � Line 2 � � � � � � � Line 3 � � � � � � Data Out Data+Parity � � Line 4 � � Line 5 Line 6 Line 7 computer 11 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Error correction example T 1-bit error ✓ 2-bit error ✗ � � � � � � � � a a b e c d Corrector 0 � � � � � � � � � � � � e d Corrector 1 � � � � � � � � ������������������������ � � c b Corrector 2 � � � � � � � � � � � � � � � � � � � � � Corrector 3 computer 12 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
Experimental setup T • SRAM error model • Benchmarks � • SPICE model of cell • SPECint, SPECfp 2000 � � � � • 8-way 2MB caches � � � • Prototype • VARIUS � � • Verilog � � � • Processor model � • Synopsys Design Compiler � � � � � � • SESC [Intel Core] • Nangate 45nm standard cell � � � • CACTI & WATTCH � • Formality � � � � ������������������������ � � Vdd Freq + Latency � Overhead � � � Nominal 0.9V 3GHz 0 � � � � used in � � � NTHigh 0.375V 460Mhz 4 � � � � � � � � simulations NTMid � 0.350V 355Mhz 4 � 0.337V 300Mhz 6 NTLow computer 13 Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors architecture research lab
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