Design Verification: Deductive Verification Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in EE-709: Testing & Verification of VLSI Circuits Lecture 37 (16 April 2013) CADSL
Formal Verification Techniques Deductive Verification (Theorem proving) Uses axioms, rules to prove system correctness Difficult and time consuming Model Checking Automatic technique to prove correctness of concurrent systems Symbolic algorithms (using BDD) Equivalence Checking Check if two circuits are equivalent CADSL 16 Apr 2012 EE-709@IITB 2
Formal Specifications In Chemistry: 2 Na + H 2 O → 2 NaOH + H 2 In Mathematics: Fermat’s Last Theorem There do not exists four positive integer, the last being greater than two, such that sum of first two, each raised to the power of fourth, equals to the third raised to the same power There do not exist integers such that x n + y n = z n Where x,y,z > 1, and n > 2 CADSL 16 Apr 2012 EE-709@IITB 3
Formal Specifications : Hardware • Specification Languages: VHDL, Verilog, HOL, Circal, …. • HDLs are not consider formal systems • VHDL has no formal mathematical semantics as part of its definition, hence, programs written in it have not been amenable to formal analysis. CADSL 16 Apr 2012 EE-709@IITB 4
Modeling in Higher-Order-Logic Developed by Gorden at Cambridge Use of predicates to represent the behaviour Predicates are functions which return result true or false Logical operators: ¬ , ∧ , ∨ , ⊃ , = Quantifiers: ∀ , ∃ Conditional statements: C ⇒ t1 t2 CADSL 16 Apr 2012 EE-709@IITB 5
Modeling in Higher-Order-Logic Extension to First order logic Variables can range over functions and predicates, called higher order and can be quantified. Principle of mathematical induction can be expressed ∀ P. P(0) ∧ ( ∀ n.P(n) ⊃ P(n+1)) ⊃ ∀ n.P(n) Functions and predicates can be the arguments and results of other functions and predicates. For example function Iterate can be define as Iterate (m,n) (f) = f(n) ∧ f(n-1) ∧ . . . . . ∧ f(m) CADSL 16 Apr 2012 EE-709@IITB 6
Formal Specification - HOL in out INV INV (in, out) = out = ¬ in ├ def DEL(in, out) = ∀ t. out(t+1) = in (t) CADSL 16 Apr 2012 EE-709@IITB 7
Formal Specification - HOL c a p D 1 b D 2 q d D 3 D 1 (a, b, p) ∧ D 2 (p,d, c,q) ∧ D 3 (q, b. d) ∃ p,q. D 1 (a, b, p) ∧ D 2 (p,d, c,q) ∧ D 3 (q, b. d) ├ def D (a, b, c, d) = ∃ p,q. D 1 (a, b, p) ∧ D 2 (p,d, c,q) ∧ D 3 (q, b. d) CADSL 16 Apr 2012 EE-709@IITB 8
Formal Specification - HOL b a SWITCH g ├ def SWITCH (g, a, b) = (g ⊃ (a = b)) SWITCH(T, F, F) holds SWITCH(F, T, F) holds SWITCH(T, T, F) doen not hold OR Gate ├ def OR (i 1 , i 2 , o) = ∀ t. o(t) = (i 1 (t) ∨ i 2 (t)) CADSL 16 Apr 2012 EE-709@IITB 9
Formal Specification - HOL Full Adder p cout a q r HA OR b HA cin sum ├ def FA (a, b, cin, cout, sum) = ∃ p, q, r. HA(a, b, p, q ) ∧ HA (q, cin, r, sum) ∧ OR (p, r, cout) CADSL 16 Apr 2012 EE-709@IITB 10
Formal Specification - HOL Ripple Carry Adder a(0) b(0) a(n-1) b(n-1) a(n-2) b(n-2) cin cout . . . . FA FA FA Out(n-1) Out(n-2) Out(0) ├ def ADD n (n) (a, b, cin, cout, sum) = (n = 0) ⇒ (cout = cin) ∃ c. ADD n (n-1) (a, b, cin, c, sum) ∧ FA ( a(n-1), b(n-1), c, cout, sum (n-1) CADSL 16 Apr 2012 EE-709@IITB 11
Formal Verification using HOL • A formal proof in HOL is constructed from axioms and inference rules • Г ├ t • Natural deduction • Conclusion t is a true proposition if all the assumptions in Г are true • Theorem CADSL 16 Apr 2012 EE-709@IITB 12
Formal Verification using HOL 1 –bit Full Adder ├ def FA (a, b, cin, cout, sum) = ∃ p, q, r. HA(a, b, p, q ) ∧ HA (q, cin, r, sum) ∧ OR (p, r, cout ) Behaviour ├ def OR (a, b, out) = ( out = (a ∨ b)) ( cout = (a ∧ b)) ∧ ├ def HA (a, b, cout, sum) = (sum = ((a ∧ ¬ b) ∨ ( ¬ a ∧ b))) ((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum)) ├ def val b = (b ⇒ 1 0) CADSL 16 Apr 2012 EE-709@IITB 13
Formal Verification using HOL ├ thm FA (a, b, cin, cout, sum) ⇒ ∃ p, q, r. HA(a, b, p, q ) ∧ HA (q, cin, r, sum ) ∧ OR (p, r, cout) ├ thm FA (a, b, cin, cout, sum) ⇒ ∃ p, q, r. ( p = (a ∧ b)) ∧ (q = ((a ∧ ¬ b) ∨ ( ¬ a ∧ b))) ∧ (r = (q ∧ cin)) ∧ (sum = ((q ∧ ¬ cin) ∨ ( ¬ q ∧ cin))) ∧ (cout = (p ∨ r)) CADSL 16 Apr 2012 EE-709@IITB 14
Formal Verification using HOL ├ thm FA (a, b, cin, cout, sum) ⇒ ∃ p, q, r. (sum = ((((a ∧ ¬ b) ∨ ( ¬ a ∧ b)) ∧ ¬ cin) ∨ (((a ∧ ¬ b) ∨ ( ¬ a ∧ b)) ∧ cin))) ∧ (cout = ((a ∧ b) ∨ (((a ∧ ¬ b) ∨ ( ¬ a ∧ b)) ∧ cin) )) CADSL 16 Apr 2012 EE-709@IITB 15
Formal Verification using HOL ├ thm FA (T, T, T, cout, sum) ⇒ ((cout = T) ∧ (sum = T)) ├ thm FA (T, T, F, cout, sum) ⇒ ((cout = T) ∧ (sum = F)) ├ thm FA (T, F, T, cout, sum) ⇒ ((cout = T) ∧ (sum = F)) ├ thm FA (T, F, F, cout, sum) ⇒ ((cout = F) ∧ (sum = T)) ├ thm FA (F, T, T, cout, sum) ⇒ ((cout = T) ∧ (sum = F)) ├ thm FA (T, T, F, cout, sum) ⇒ ((cout = F) ∧ (sum = T)) ├ thm FA (F, F, T, cout, sum) ⇒ ((cout = F) ∧ (sum = T)) ├ thm FA (F, F, F, cout, sum) ⇒ ((cout = F) ∧ (sum = F)) CADSL 16 Apr 2012 EE-709@IITB 16
Formal Verification using HOL ├ thm ∀ a, b, cin, cout, sum . FA (a, b, cin, cout, sum) ⇒ ((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum)) CADSL 16 Apr 2012 EE-709@IITB 17
Formal Specification - HOL Ripple Carry Adder A(0) b(0) a(n) b(n) a(n-2) b(n-2) cin cout . . . . FA FA FA Out(n) Out(n-2) Out(0) ├ def ADD n (n) (a, b, cin, cout, sum) = (n = 0) ⇒ (cout = cin) ∃ c. ADD n (n-1) (a, b, cin, c, sum) ∧ FA ( a(n-1), b(n-1), c, cout, sum (n-1) CADSL 16 Apr 2012 EE-709@IITB 18
Formal Verification using HOL 1-bit Full Adder ├ thm ∀ a, b, cin, cout, sum . FA (a, b, cin, cout, sum) ⇒ ((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum)) CADSL 16 Apr 2012 EE-709@IITB 19
Formal Verification using HOL Valn - value of first n bits of a bus ├ def val n b = ((n = 0) ⇒ 0 (( 2 n-1 x (val (b (n-1) ))) + (valn (n-1) b))) Coorectness of n-bit adder can be expressed as ((valn n a) + (valn n b) + (val cin)) = ( (2 n x (val cout)) + (valn n sum)) Using inductive proof strategy, it is sufficient to prove for • Basis step, n=0 • Inductive step, n+1 CADSL 16 Apr 2012 EE-709@IITB 20
Formal Verification using HOL Basis Step: ADDn 0 (a, b, cin, cout, sum) ⇒ (((valn 0 a) + (valn 0 b) + (val cin)) = ( (2 0 x (val cout)) + (valn n sum))) ├ thm ADDn 0 (a, b, cin, cout, sum) = (cout = cin) (cout = cin) ⇒ ((0 + 0 + (val cin)) = ( (2 0 x (val cout)) + 0 ) ) CADSL 16 Apr 2012 EE-709@IITB 21
Formal Verification using HOL Inductive Step: Lemma: ├ tthm ADDn (n+1) (a, b, cin, cout, sum) = ∃ c. ADD n n (a, b, cin, c, sum) ∧ FA ( a n, b n, c, cout, sum n) Inductive hypothesis: ((valn n a) + (valn n b) + (val cin)) = ( (2 n x (val c)) + (valn n sum)) Correctness theorem for 1-bit adder ((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum)) CADSL 16 Apr 2012 EE-709@IITB 22
Formal Verification using HOL Inductive Step: (2 n x ((val a) + (val b) + (val c)) )= ( 2 n x( (2 x (val cout)) + (val sum))) ├ tthm ∀ n m p q. (n = m) ∧ (p = q) ⇒ ((n+p) = (m +q)) ((2 n x ((val a) + (val b) + (val c)) ) + ((valn n a) + (valn n b) + (val cin)) ) = (( 2 n x( (2 x (val cout)) + (val sum))) + ( (2 n x (val c)) + (valn n sum))) CADSL 16 Apr 2012 EE-709@IITB 23
Formal Verification using HOL ├ thm ∀ b. (2 n x ((val b n))) + (valn n b) ) = valn (n-1) b ((valn (n+1) a) + (valn (n+1) b) + (val cin)) = ( (2 n+1 x (val c)) + (valn (n+1) sum)) Hence ├ tthm ∀ n a b cin cout sum. ADDn n (a, b, cin, cout, sum) ⇒ ((valn n a) + (valn n b) + (val cin)) = ( (2 n x (val cout)) + (valn n sum)) CADSL 16 Apr 2012 EE-709@IITB 24
Thank You CADSL 16 Apr 2012 EE-709@IITB 25
Problem The following ordered vector set is being applied to the Random Access Circuit to minimize the test application time. Compute the order of bit change (address order) for the application of next test which can minimize the test time. Assume you have availability of 4 PI pins. Test PPI PPO T1 00100 00101 T2 00101 00110 T4 00111 01011 T3 11010 11010 CADSL 16 Apr 2012 EE-709@IITB 26
CADSL 16 Apr 2012 EE-709@IITB 27
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