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Design Verification: Deductive Verification Virendra Singh - - PowerPoint PPT Presentation

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Design Verification: Deductive Verification Virendra Singh Associate Professor C omputer A rchitecture and D ependable S ystems L ab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/

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CADSL

Design Verification: Deductive Verification

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-709: Testing & Verification of VLSI Circuits

Lecture 37 (16 April 2013)

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2

Formal Verification

Techniques  Deductive Verification (Theorem proving)

  • Uses axioms, rules to prove system correctness
  • Difficult and time consuming

 Model Checking

  • Automatic technique to prove correctness of

concurrent systems

  • Symbolic algorithms (using BDD)

 Equivalence Checking

  • Check if two circuits are equivalent

16 Apr 2012 EE-709@IITB

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CADSL

16 Apr 2012 EE-709@IITB 3

Formal Specifications

In Chemistry: 2 Na + H2O → 2 NaOH + H2 In Mathematics: Fermat’s Last Theorem

There do not exists four positive integer, the last being greater than two, such that sum of first two, each raised to the power of fourth, equals to the third raised to the same power

There do not exist integers such that xn + yn = zn Where x,y,z > 1, and n > 2

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CADSL

16 Apr 2012 EE-709@IITB 4

Formal Specifications : Hardware

  • Specification Languages: VHDL, Verilog,

HOL, Circal, ….

  • HDLs are not consider formal systems
  • VHDL has no formal mathematical semantics

as part of its definition, hence, programs written in it have not been amenable to formal analysis.

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CADSL

16 Apr 2012 EE-709@IITB 5

Modeling in Higher-Order-Logic

  • Developed by Gorden at Cambridge
  • Use of predicates to represent the behaviour
  • Predicates are functions which return result true
  • r false

 Logical operators: ¬ , ∧ , ∨ , ⊃ , =  Quantifiers: ∀ , ∃ Conditional statements: C ⇒ t1  t2

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CADSL

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Modeling in Higher-Order-Logic

Extension to First order logic

  • Variables can range over functions and

predicates, called higher order and can be

  • quantified. Principle of mathematical induction can

be expressed

  • ∀P. P(0) ∧ (∀n.P(n) ⊃ P(n+1)) ⊃ ∀n.P(n)
  • Functions and predicates can be the arguments

and results of other functions and predicates. For example function Iterate can be define as

  • Iterate (m,n) (f) = f(n) ∧ f(n-1) ∧ . . . . . ∧ f(m)
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CADSL

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Formal Specification - HOL

INV (in, out) = out = ¬ in

├ def DEL(in, out) = ∀ t. out(t+1) = in (t)

INV in

  • ut
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CADSL

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Formal Specification - HOL

D1 D2 D3 a b q p d c D1(a, b, p) ∧ D2(p,d, c,q) ∧ D3(q, b. d)

∃ p,q. D1(a, b, p) ∧ D2(p,d, c,q) ∧ D3(q, b. d)

├ def D (a, b, c, d) = ∃ p,q. D1(a, b, p) ∧ D2(p,d, c,q) ∧ D3(q, b. d)

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CADSL

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Formal Specification - HOL

├ def SWITCH (g, a, b) = (g ⊃ (a = b))

SWITCH(T, F, F) holds SWITCH(F, T, F) holds SWITCH(T, T, F) doen not hold OR Gate ├ def OR (i1, i2, o) = ∀ t. o(t) = (i1(t) ∨ i2(t))

SWITCH b a g

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CADSL

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Formal Specification - HOL

├ def FA (a, b, cin, cout, sum) = ∃ p, q, r. HA(a, b, p, q) ∧

HA (q, cin, r, sum) ∧ OR (p, r, cout)

HA HA OR a b cin q p sum r cout

Full Adder

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CADSL

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Formal Specification - HOL

├ def ADDn (n) (a, b, cin, cout, sum) = (n = 0) ⇒ (cout = cin) 

∃ c. ADDn (n-1) (a, b, cin, c, sum) ∧ FA ( a(n-1), b(n-1), c, cout, sum (n-1)

FA FA FA a(n-1) a(n-2) a(0) b(n-1) b(n-2) b(0) cin Out(0) cout Out(n-1) Out(n-2) . . . .

Ripple Carry Adder

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CADSL

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Formal Verification using HOL

  • A formal proof in HOL is constructed from

axioms and inference rules

  • Г ├ t
  • Natural deduction
  • Conclusion t is a true proposition if all

the assumptions in Г are true

  • Theorem
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CADSL

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Formal Verification using HOL

1 –bit Full Adder

├ def FA (a, b, cin, cout, sum) = ∃ p, q, r. HA(a, b, p, q) ∧ HA (q, cin, r, sum) ∧ OR (p, r, cout)

Behaviour ├ def OR (a, b, out) = ( out = (a ∨ b)) ├ def HA (a, b, cout, sum) = ( cout = (a ∧ b)) ∧ (sum = ((a ∧ ¬ b) ∨ (¬ a ∧ b))) ((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum)) ├ def val b = (b ⇒ 1 0)

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CADSL

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Formal Verification using HOL

├ thm FA (a, b, cin, cout, sum) ⇒ ∃ p, q, r. HA(a, b, p, q) ∧

HA (q, cin, r, sum) ∧ OR (p, r, cout)

├ thm FA (a, b, cin, cout, sum) ⇒ ∃ p, q, r.

( p = (a ∧ b)) ∧ (q = ((a ∧ ¬ b) ∨ (¬ a ∧ b))) ∧ (r = (q ∧ cin)) ∧ (sum = ((q ∧ ¬ cin) ∨ (¬ q ∧ cin))) ∧ (cout = (p ∨ r))

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CADSL

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Formal Verification using HOL

├ thm FA (a, b, cin, cout, sum) ⇒ ∃ p, q, r.

(sum = ((((a ∧ ¬ b) ∨ (¬ a ∧ b)) ∧ ¬ cin) ∨ (((a ∧ ¬ b) ∨ (¬ a ∧ b)) ∧ cin))) ∧ (cout = ((a ∧ b) ∨ (((a ∧ ¬ b) ∨ (¬ a ∧ b)) ∧ cin) ))

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CADSL

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Formal Verification using HOL

├ thm FA (T, T, T, cout, sum) ⇒ ((cout = T) ∧ (sum = T)) ├ thm FA (T, T, F, cout, sum) ⇒ ((cout = T) ∧ (sum = F)) ├ thm FA (T, F, T, cout, sum) ⇒ ((cout = T) ∧ (sum = F)) ├ thm FA (T, F, F, cout, sum) ⇒ ((cout = F) ∧ (sum = T)) ├ thm FA (F, T, T, cout, sum) ⇒ ((cout = T) ∧ (sum = F)) ├ thm FA (T, T, F, cout, sum) ⇒ ((cout = F) ∧ (sum = T)) ├ thm FA (F, F, T, cout, sum) ⇒ ((cout = F) ∧ (sum = T)) ├ thm FA (F, F, F, cout, sum) ⇒ ((cout = F) ∧ (sum = F))

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CADSL

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Formal Verification using HOL

├ thm ∀ a, b, cin, cout, sum . FA (a, b, cin, cout, sum) ⇒

((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum))

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CADSL

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Formal Specification - HOL

├ def ADDn (n) (a, b, cin, cout, sum) = (n = 0) ⇒ (cout = cin) 

∃ c. ADDn (n-1) (a, b, cin, c, sum) ∧ FA ( a(n-1), b(n-1), c, cout, sum (n-1)

FA FA FA a(n) a(n-2) A(0) b(n) b(n-2) b(0) cin Out(0) cout Out(n) Out(n-2) . . . .

Ripple Carry Adder

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CADSL

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Formal Verification using HOL

├ thm ∀ a, b, cin, cout, sum . FA (a, b, cin, cout, sum) ⇒

((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum))

1-bit Full Adder

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CADSL

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Formal Verification using HOL

Valn - value of first n bits of a bus ├ def val n b = ((n = 0) ⇒ 0 (( 2n-1 x (val (b (n-1) ))) + (valn (n-1) b)))

Coorectness of n-bit adder can be expressed as

((valn n a) + (valn n b) + (val cin)) = ( (2n x (val cout)) + (valn n sum)) Using inductive proof strategy, it is sufficient to prove for

  • Basis step, n=0
  • Inductive step, n+1
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CADSL

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Formal Verification using HOL

Basis Step:

ADDn 0 (a, b, cin, cout, sum) ⇒ (((valn 0 a) + (valn 0 b) + (val cin)) = ( (20 x (val cout)) + (valn n sum)))

├ thm ADDn 0 (a, b, cin, cout, sum) = (cout = cin)

(cout = cin) ⇒ ((0 + 0 + (val cin)) = ( (20 x (val cout)) + 0 ) )

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CADSL

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Formal Verification using HOL

Inductive Step:

Lemma: ├ tthm ADDn (n+1) (a, b, cin, cout, sum) = ∃ c. ADDn n (a, b, cin, c, sum) ∧ FA ( a n, b n, c, cout, sum n) Inductive hypothesis: ((valn n a) + (valn n b) + (val cin)) = ( (2n x (val c)) + (valn n sum)) Correctness theorem for 1-bit adder ((val a) + (val b) + (val c)) = ( (2 x (val cout)) + (val sum))

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CADSL

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Formal Verification using HOL

Inductive Step:

(2n x ((val a) + (val b) + (val c)) )= ( 2n x( (2 x (val cout)) + (val sum))) ├ tthm ∀ n m p q. (n = m) ∧ (p = q) ⇒ ((n+p) = (m +q)) ((2n x ((val a) + (val b) + (val c)) ) + ((valn n a) + (valn n b) + (val cin)) ) = (( 2n x( (2 x (val cout)) + (val sum))) + ( (2n x (val c)) + (valn n sum)))

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Formal Verification using HOL

├ thm ∀ b. (2n x ((val b n))) + (valn n b) ) = valn (n-1) b ((valn (n+1) a) + (valn (n+1) b) + (val cin)) = ( (2n+1 x (val c)) + (valn (n+1) sum))

Hence

├ tthm ∀ n a b cin cout sum. ADDn n (a, b, cin, cout, sum) ⇒ ((valn n a) + (valn n b) + (val cin)) = ( (2n x (val cout)) + (valn n sum))

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Thank You

16 Apr 2012 EE-709@IITB 25

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Problem

The following ordered vector set is being applied to the Random Access Circuit to minimize the test application time. Compute the order of bit change (address order) for the application of next test which can minimize the test time. Assume you have availability of 4 PI pins.

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Test PPI PPO T1 00100 00101 T2 00101 00110 T4 00111 01011 T3 11010 11010

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CADSL

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