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Andrew Frey Western Washington University Electronics Engineering - - PowerPoint PPT Presentation
Andrew Frey Western Washington University Electronics Engineering - - PowerPoint PPT Presentation
Andrew Frey Western Washington University Electronics Engineering Technology 2010 MCU: Freescale 9S12C32 32kBytes Flash EEPROM, 2kBytes RAM 24MHz Bus Frequency Memory Requirements <10kBytes ROM 1kByte RAM Resources
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Kernel
TimeSlice 10ms period 4 Tasks
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CPLD: Xilinx XC2C256
256 Macrocells, 16 Function Blocks System Frequency: 1MHz
Required Resources
~30 Macrocells
Resources Used:
8 GPIO pins
Hierarchal VHDL Design
9 VHDL modules (8 for SPI implementation)
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Different
States correspond to users actions
Only 1
state(sleep mode) not user defined
First Code Entered Main Menu
User Code Management
Unlock Lock Sleep Mode
Button Pressed Inactivity Period Enter Code
*
#
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WaitForSlice
Time Slice Scheduler
10ms period
KeyTask
Checks for keypress
Period: 10ms(sporadic)
Execution Time: ~50µs
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UITask
Handles input from KeyTask Updates the LCD screen Saves user codes Period: 20ms(sporadic) Execution Time: ~2ms
RFTask
Configures Registers and sends data packets if valid
code has been entered
Period: 100ms Execution Time: ~500µs
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Keypad I/O KeyTask() Key.c KeyInit() GetKey() WKDoorLock.c Key KeyFlag
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WKDoorLock.c UITask() Key.c LD4Bit.c
LcdDispStrg() GetKey()
Key
FlashSaveCode()
SaveCode ProgFlash.c RFModules.c RFTask()
GoodCode
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RFTask() RFModules.c WKDoorLock.c UITask() Startup
nRF24L01Init() TxConfig() GoodCode
nRF24L01+
LockMsg()
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L=Execution Time/Period Lpeak = 50µs/10ms + 2ms/20ms + .5ms/100ms
= 11%
Lavg = 4% based on amount of time in between uses
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Module Tasks Functions Data WKDoorLock.c WaitFor Slice() UITask()
- MsgOut
Code LCD4Bit.c
- Lcd4BitInit()
RFModules.c RFTask() nRF24L01Init() TxConfig() LockMsg() Good_Code Key.c KeyTask() GetKey() KeyInit() Key ProgFlash.c
- FlashSaveCode()
UserCode
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Detect_and_signal.vhd
Decodes incoming Signal Sends signal to motor driver ~50-75 Macrocells used
Spi_interface.vhd
The master program for SPI implementaion Consists of 8 other VHDL modules ~30 Macrocells used
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nRF24L01+ Spi_interface Spi_master.vhd Main.vhd
Detect/Decode
Motor Driver
MotorBF
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Macrocell usage:
~30/256 = 12%
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