Analysis and Synthesis of Communication-Intensive Heterogeneous - - PowerPoint PPT Presentation

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Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems

Paul Pop Computer and Information Science Dept. Linköpings universitet

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Introduction

System-level design and modeling

Conditional process graph

The system platform

Time-driven vs. event-driven systems

• Communication-intensive heterogeneous real-time systems

Time-driven systems

Scheduling and bus access optimization Incremental mapping

Event-driven systems

Schedulability analysis and bus access optimization Incremental mapping

Multi-Cluster Systems

Schedulability analysis and bus access optimization Frame packing

• Summary of contributions

Outline

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General purpose systems Embedded systems

Microprocessor market shares

Embedded Systems

Communication-intensive heterogeneous real-time systems

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Embedded Systems Characteristics

Dedicated functionality (not general purpose computers)

Embedded into a host system Complex architectures

Embedded systems design constraints

Correct functionality Performance, timing constraints: real-time systems Development cost, unit cost, size, power, flexibility, time-to- prototype, time-to-market, maintainability, correctness, safety, etc.

Difficult to design, analyze and implement

System-level design Reuse and flexibility

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System-Level Design

System specification Software model Hardware model Software generation Hardware synthesis Software blocks Hardware blocks Prototype Fabrication

System-level design tasks

In this thesis

• Scheduling
• Bus access optimization
• Mapping

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P4 P4 P5 P5 P7 P7 P13 P13 P15 P15

First processor Second processor ASIC

C C D D P0 P18 P1 P1 P2 P2 P3 P3 P6 P6 P8 P8 P9 P9 P10 P10 P11 P11 P12 P12 P14 P14 P16 P16 P17 P17 C K K

Application Modeling #1

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P4 P4 P5 P5 P7 P7 P13 P13 P15 P15

First processor Second processor ASIC

C C D D P0 P18 P1 P1 P2 P2 P3 P3 P6 P6 P8 P8 P9 P9 P10 P10 P11 P11 P12 P12 P14 P14 P16 P16 P17 P17 C K K

Application Modeling #2

P0 P18 P1 P2 P3 P6 P8 P9 P10 P11 P12 P14 P16 P17

Subgraph corresponding to D∧C∧K

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I/O Interface

• Comm. controller

CPU RAM ROM ASIC

Hardware Platform

S0 S1 S2 SG S0 S1 S2 SG TDMA Round Cycle of two rounds Slot

Time Triggered Protocol (TTP)

• Bus access scheme:

time-division multiple-access (TDMA)

• Schedule table located in each TTP

controller: message descriptor list (MEDL)

Controller Area Network (CAN)

• Priority bus, collision avoidance
• Highest priority message

wins the contention

• Priorities encoded in the frame identifier

Cluster:

• ne network

Gateway

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Distributed Safety-Critical Applications

... ...

Distributed applications are difficult to... Analyze (e.g., guaranteeing timing constraints) Design (e.g., efficient implementation) Distributed applications

On a single cluster On several clusters

Motivation

Reduce costs: use resources efficiently Requirements: close to sensors/ actuators

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Event-Driven vs. Time-Driven Systems

• Event-driven systems

Activation of processes is done at the occurrence of significant events Scheduling event-triggered activities

Fixed-priority preemptive scheduling Response time analysis: calculate worst-case response times for each process Schedulability test: response times smaller than the deadlines

• Time-driven systems

Activation of processes is done at predefined points in time Scheduling time-triggered activities

Static cyclic non-preemptive scheduling Building a schedule table: static cyclic scheduling (e.g., list scheduling)

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• Introduction

System-level design and modeling

Conditional process graph

The system platform

Time-triggered vs. event-triggered

• Communication-intensive heterogeneous real-time systems

Time-driven systems

Scheduling and bus access optimization Incremental mapping

Event-driven systems

Schedulability analysis and bus access optimization Incremental mapping

Multi-Cluster Systems

Schedulability analysis and bus access optimization Frame packing

• Summary of contributions

Outline

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Scheduling and Bus Access Optimization

Input

Safety-critical application: set of conditional process graphs

The worst-case execution time of each process The size of each messages

The system architecture and mapping are given

Time-driven systems

Single-cluster architecture Time-triggered protocol Non-preemptive static cyclic scheduling

Output

Design implementation such that the application is schedulable and execution delay is minimized

Local schedule tables for each node The sequence and size of the slots in a TDMA round The MEDL (schedule table for messages) for each TTP controller

Communication infrastructure parameters Time-driven systems

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P1 P1 P4 P4 P2 P2 P3 P3 m1 m2 m3 m4

S1 S0 Round 1 Round 2 Round 3 Round 4 Round 5 P1 P4 P2 m1 m2 m3 m4 P3

24 ms

Round 1 P1 Round 2 Round 3 Round 4 S1 S0 m1 m2 m3 m4 P2 P3 P4

22 ms

Round 1 Round 2 Round 3 S1 S0 P2 P3 P4 P1 m1 m2 m3 m4

20 ms

Scheduling and Optimization Example

Time-driven systems

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Scheduling and Optimization Strategy

• List scheduling based algorithm

The scheduling algorithm has to take into consideration the TTP Priority function for the list scheduling

• Bus access optimization heuristics

Greedy heuristic, two variants

Greedy 1 tries all possible slot lengths Greedy 2 uses feedback from the scheduling algorithm

Simulated Annealing

Produces near-optimal solutions in a very large time Cannot be used inside a design space exploration loop Used as the baseline for comparisons

Straightforward solution

Finds a schedulable application Does not consider the optimization of the design Time-driven systems

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10 20 30 40 50 60 80 160 240 320 400 Straightforward solution Greedy 1 Greedy 2

Number of processes Average Percentage Deviation [%]

Can We Improve the Schedules?

Baseline: Simulated Annealing

Cost function: schedule length

Case study

Vehicle cruise controller Used throughout the thesis

Time-driven systems

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S1 S0 Round 1 Round 2 Round 3 Round 4 Round 5 P1 P4 P2 m1 m2 m3 m4 P3

P1 P4 P2 P3

N1 N2 N1 N2 Bus

“Classic” Mapping and Scheduling Example

Time-driven systems

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Start from an already existing system with applications

In practice, very uncommon to start from scratch

Implement new functionality on this system (increment)

As few as possible modifications of the existing applications, to reduce design and testing time Plan for the next increment: It should be easy to add functionality in the future

Incremental Design Process

Time-driven systems

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Minimal modifications are performed to the existing applications

Existing applications

N-1

Map and schedule so that the future applications will have a chance to fit

Current applications

N

Do not exist yet at Version N!

Future applications

Version N+1

Incremental Mapping and Scheduling

Time-driven systems

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Incremental Mapping and Scheduling

• Input

A set of existing applications modeled using process graphs A current application to be mapped modeled using process graphs

Each process graph in an application has its own period and deadline Each process has a potential set of nodes to be mapped on and a WCET

Characteristics of the future applications The system architecture is given

• Output

A mapping and scheduling of the current application, such that:

Requirement (a) constraints of the current application are satisfied and minimal modifications are performed to the existing applications Requirement (b) new future applications can be mapped on the resulted system Time-driven systems

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Existing application Current application Future application The future application does not fit! (a) (b)

Mapping and Scheduling Example

Time-driven systems

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Mapping and Scheduling Strategies

Time-driven systems

Design optimization problem

Design criteria reflect the degree to which a design supports an incremental design process Design metrics quantify the degree to which the criteria are met

Heuristics to improve the design metrics

Ad-hoc approach

Little support for incremental design

Mapping Heuristic

Iteratively performs design transformations that improve the design

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10 20 30 40 50 60 70 80 90 100 40 80 160 240 MH AH % of future applications mapped existing applications: 400, future application: 80 Number of processes in the current application Are the mapping strategies proposed facilitating the implementation of future applications?

Existing application Current application Future application

Can We Support Incremental Design?

Time-driven systems

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• Introduction

System-level design and modeling

Conditional process graph

The system platform

Time-triggered vs. event-triggered

• Communication-intensive heterogeneous real-time systems

Time-driven systems

Scheduling and bus access optimization Incremental mapping

Event-driven systems

Schedulability analysis and bus access optimization Incremental mapping

Multi-Cluster Systems

Schedulability analysis and bus access optimization Frame packing

• Summary of contributions

Outline

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Scheduling and Bus Access Optimization

Input

Safety-critical application: set of conditional process graphs

The worst-case execution time of each process The size of each messages

The system architecture and mapping are given

Event-driven systems

Single cluster architecture Time-triggered protocol Fixed-priority preemptive scheduling

Output

Worst-case response times (schedulability analysis) Design implementation such that the application is schedulable and execution delay is minimized

The sequence and size of the slots in a TDMA round The MEDL (schedule table for messages) for each TTP controller

Communication infrastructure parameters Event-driven systems

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Conditional Process Graph Scheduling

P3 P3 P5 P5 C P0 P0 P1 P1 P6 P6 P2 P2 P7 P7 P4 P4 P8 P8 C 27 30 24 19 25 30 22

G1

P11 P11 P12 P12 P9 P9 P10 P10 25 32

G2

Worst Case Delays CPG Not considering conditions Considering conditions G1 120 100 G2 82 82

Deadline: 110

Event-driven systems

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• 1. Single message per frame, allocated statically:

Static Single Message Allocation

• 2. Several messages per frame, allocated statically:

Static Multiple Message Allocation

m1 m2 m5 m3 m4 Round 1 Round 2 Round 3 S0 S1

messages are dynamically produced by the processes frames are statically determined by the MEDL

• 3. Several messages per frame, allocated dynamically:

Dynamic Message Allocation

• 4. Several messages per frame, split into packets, allocated dynamically

Dynamic Packets Allocation

Scheduling of Messages using the TTP

Event-driven systems

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Compartison…

Dynamic Messages Single Message Dynamic Packets Multiple Messages

4 8 12 16 80 160 240 320 400

Average Percentage Deviation [%] Number of processes Cost function: degree of schedulability

Event-driven systems

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m1 m2 P1 P2 P3 m2 m1 P1 P2 P3

Swapping m1 with m2: all processes meet their deadlines.

m1 m2 P1 P2 P3

Putting m1 and m2 in the same slot: all processes meet their deadline, the communication delays are reduced. Process P2 misses its deadline!

Optimizing Bus Access (Static Allocation)

Event-driven systems

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• Introduction

System-level design and modeling

Conditional process graph

The system platform

Time-triggered vs. event-triggered

• Communication-intensive heterogeneous real-time systems

Time-driven systems

Scheduling and bus access optimization Incremental mapping

Event-driven systems

Schedulability analysis and bus access optimization Incremental mapping

Multi-Cluster Systems

Schedulability analysis and bus access optimization Frame packing

• Summary of contributions

Outline

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Schedulability Analysis and Optimization

• Input

An application modeled as a set of process graphs Each process has an worst case execution time, a period, and a deadline Each message has a known size The system architecture and the mapping of the application are given

• Multi-cluster systems

Two-cluster architecture Time-triggered cluster

Time-triggered protocol Non-preemptive static cyclic scheduling

Event-triggered cluster

Controller area network protocol Fixed-priority preemptive scheduling Multi-cluster systems

... ...

• Output

Worst case response times and bounds on the buffer sizes Design implementation such that the application is schedulable and buffer sizes are minimized

Schedule table for TT processes Priorities for ET processes Schedule table for TT messages Priorities for ET messages TT bus configuration (TDMA slot sequence and sizes) Communication infrastructure parameters System configuration parameters

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Multi-Cluster Scheduling

• Scheduling cannot be addressed separately for each type of cluster
• The inter-cluster communication creates a circular dependency:

TTC static schedules (offsets) ⇒ ETC response times ETC response times ⇒ TTC schedule table construction

Application, Mapping, Architecture TT Bus Configuration Priorities Schedule Tables Response times Static Scheduling Multi-Cluster Scheduling Offsets Response Times Offset earliest possible start time for an event-triggered activity Bounds

• n the

buffer sizes Response Time Analysis Multi-cluster systems

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Optimization Example #1

TTP CAN N1 NG N2

P2 P3 O3 O2 m1 m3 m2

SG S1 SG

P1

S1 SG

P4

Deadline missed!

...

...

Multi-cluster systems

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Optimization Example #2

TTP CAN N1 NG N2

P2 P3 O3 O2 m1 m3 m2

SG S1 SG

P1

S1 SG

P4

Deadline missed! TTP CAN N1 NG N2

O3 O2 m1 m3 m2

S1 SG SG S1 SG

P1 P4 P2 P3

Deadline met

Transformation: S1 is the first slot, m1 and m2 are sent sooner

...

...

Multi-cluster systems

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Optimization Example #3

TTP CAN N1 NG N2

P2 P3 O3 O2 m1 m3 m2

SG S1 SG

P1

S1 SG

P4

Deadline missed! TTP CAN N1 NG N2

O3 O2 m1 m3 m2

S1 SG SG S1 SG

P1 P4 P2 P3

Deadline met

Transformation: S1 is the first slot, m1 and m2 are sent sooner

N1 NG N2

O3 O2 m1 m3 m2

SG S1 SG S1

P1 P2 P3 P4

TTP CAN Deadline met

Transformation: P2 is the high priority process on N2

...

...

Multi-cluster systems

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Optimization Strategies

• OptimizeSchedule

Synthesizes the communication and assigns priorities to obtain a schedulable application Based on a greedy approach

Cost function: degree of schedulability

• OptimizeBuffers

Synthesizes the communication and assigns priorities to reduce the total buffer size Based on a hill-climbing heuristic

Cost function: total buffer size

• Straightforward solution

Finds a schedulable application Does not consider the optimization of the design

Multi-cluster systems

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Can We Improve Schedulability?

20 40 60 80 100 80 160 240 320 400

Average Percentage Deviation [%] Number of processes

120

Simulated Annealing

Near-optimal values for the degree of schedulability

Straightforward solution

Does not perform optimizations

Cost function: degree of schedulability OptimizeSchedule? OptimizeSchedule

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Can We Reduce Buffer Sizes?

2k 4k 6k 8k 10k 80 160 240 320 400

Average total buffer size [k] Number of processes Simulated Annealing

Near-optimal values for the total buffer size

OptimizeSchedule

Does not optimize the total buffer size

Cost function: total buffer size OptimizeBuffers? OptimizeBuffers

Multi-cluster systems

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• Introduction

System-level design and modeling

Conditional process graph

The system platform

Time-triggered vs. event-triggered

• Communication-intensive heterogeneous real-time systems

Time-driven systems

Scheduling and bus access optimization Incremental mapping

Event-driven systems

Schedulability analysis and bus access optimization Incremental mapping

Multi-Cluster Systems

Schedulability analysis and bus access optimization Frame packing

Summary of contributions

Outline

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Time-driven systems

Static scheduling strategy Optimization strategies for the synthesis of the bus access scheme Mapping and scheduling within an incremental design process

Event-driven systems

Schedulability analysis Optimization strategies for the synthesis of the bus access scheme Mapping and scheduling within an incremental design process

Multi-cluster systems

Schedulability analysis for multi-cluster systems Optimization heuristics for system synthesis: minimal buffer sizes needed to run a schedulable application Frame-packing optimization heuristics

Thesis Contributions