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An Integrated Modeling, Synthesis and Verification Methodology - - PowerPoint PPT Presentation

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HLS Based HW and SW Co-Design of Complex IP Subsystems An Integrated Modeling, Synthesis and Verification Methodology Xiaojian Liu Greg Smith June 4th, 2013 David Hansen Jeff Wong Louie Lee PAGE 1 2 Author Page Xiaojian Liu,

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SLIDE 1

PAGE 1

HLS Based HW and SW Co-Design

  • f Complex IP Subsystems

An Integrated Modeling, Synthesis and Verification Methodology

Xiaojian Liu Greg Smith David Hansen Jeff Wong Louie Lee June 4th, 2013

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SLIDE 2

Author Page

  • Xiaojian Liu, xiaojian@qti.qualcomm.com
  • Greg Smith, smithg@qti.qualcomm.com
  • David Hansen, hansend@qti.qualcomm.com
  • Jeff Wong, wjeff@qti.qualcomm.com
  • Louie Lee, louielee@qti.qualcomm.com
  • Affiliation: Qualcomm Inc.

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SLIDE 3

Outline

  • SoC and IP Design Challenges
  • Mastering Complex IP Subsystem: HW and SW Co-Design
  • Key to HW & SW Co-Design: HL Modeling & Synthesis
  • HL Modeling, Synthesis & Optimization: From Transaction

Accuracy to Cycle Accuracy

  • Verification & Validation: Moving to High Level
  • Key to Design Productivity: An Integrated HL Design Flow
  • Design Examples
  • Remarks

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SLIDE 4

SoC and IP Design Challenges

  • SoC capacity still increasing
  • Requirements for additional features continues to grow
  • Complex IP Subsystem itself is a “deeply” embedded system

with hardware and software

  • HW/SW Co-Development
  • IP subsystem Design Team is typically “small” compared to a

full SoC design team

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D-Bus C-Bus

CPU GPU Video Codec Audio Proc Video Post- Proc Camera Modem Video Display IO Interface

SoC and IP SS

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SLIDE 5

Master Complexity at IP Subsystem Level

  • HW/SW Co-Design

5 IP Algo IP Arch SW Design Virtual Platform HW Design

  • IP design requires a different design approach: a “high

performance” and “high efficiency” HW and SW co-design methodology, on a “closed” platform.

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SLIDE 6

Key to HW & SW Co-Design: HL Modeling & Synthesis

  • Models:
  • Hardware (datapath and micro-processors)
  • Software (control and datapath processing)
  • Virtual Platform (transactional connectivity)
  • High Performance:
  • Must use high level (C) hardware model for fast simulation speed
  • Must use high level (C) virtual platform for fast simulation speed
  • Must use high layer (C) software code for fast simulation speed
  • High Efficiency = Automated Design Flow (HL to LL):
  • High level (C) model must be synthesizable to RTL and below
  • Virtual platform must support multi-level of modeling accuracy:

functional, multi-level transactional, and cycle accuracy

  • High layer SW (C) code must interface with low layer driver code

and higher layer App code seamlessly

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SLIDE 7

USE (unified software environment): Multi-layer seamless context aware interface Platform VIP library ML TL modeling HL/TL verification

HL Modeling, Synthesis & Optimization

7 C2RTL synthesis PPA optimization HL/CA verification Transactional FEC IP Algo IP Arch Functional SW Multi-Level Transactional SS Platform

  • Ref. C Model

RTL Platfm Blk Design RTL SS Integration RTL SS Platform Blk Driver & API Platfm Driver Platfm API Synth C Blk / uP Descript.

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SLIDE 8

High Level Synthesis & Optimization: An Enabling Technology

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C to RTL Synthesis & PPA Optimization Process Independent; Scheduling; Resource Sharing; Top-down Hier. Synthesis Bottom-Up Synthesis; ECO C++/SystemC/RTL; Area/Timing Estimation; Untimed synth “C” RTL Sequential Clock Gating; Memory Gating; Vt and Power Domain Aware; Power Estimation; TV uProcessor Synthesis

uP Description

ISS Compiler TC TLM RTL

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SLIDE 9

High Level Synthesis & Optimization:

  • - From Transaction Accuracy to Cycle Accuracy
  • “Forward” Synthesis
  • Untimed (synth) “C” design
  • Scheduling -> “timed” design
  • Logic optimization -> RTL design
  • Adding RTL “transactors” -> RTL interfaces/ports/channels
  • -> Building blocks for RTL SS design
  • “Backward” Analysis
  • Add HL (SysC) “transactor” to “untimed” C design
  • Add TLM wrapper to the top HL “transactor” if required
  • -> Building blocks for ML Transactional SS performance modeling
  • “Feedback” Loop
  • Micro-architecture optimization
  • Performance analysis
  • Hardware verification
  • Software validation

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TS TS TS TS TS TS TS TS TS/TLM TS/TLM

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SLIDE 10
  • Fast to build & to run
  • Support iterative design

approach

  • Support ML transactions

Verification & Validation: Moving to High Level

  • Subsystem Level

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Functional SW Multi-Level Transactional SS Platform

  • Ref. C Model

RTL Datapath Design uP RTL Design RTL SS Platform Driver & API Platfm Driver Platfm API Synth C Blks Input Stimulus Test Vectors

  • Simplify RTL TB environm.
  • Seamless integration with

existing RTL methodology

  • Traffic performance analys.
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SLIDE 11

Verification & Validation: Moving to High Level

  • Block Level

11 C2RTL Synthesis

Synth C Model C Inline Coverage Model Offline RTL Coverage Model RTL Code

Automated RTL P/F and Cov Verification Relevant observation points are always either in IO library or as C variables

Transactors

C Testbench

RTL Simulator C Simulations P/F and Cov

Transactional C2RTL FEC

Transactors

Automated C2RTL Transactional FEC

Ref C Model

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SLIDE 12

An Integrated HL Design Methodology: Key to High Design Productivity

12 Synthesis Verification Modeling Design Algorithm Design Architecture HW/SW Partitions AlgoC Model Ref C Model SynC Model uP ISA Model uP ISS Model IPQ Validation

Synth RTL Core

Algo Evaluation ISA Verification VC Model

IP Charac- terization

uP RTL Verification Synth RTL Verification

RefC/SynC Verification An integrated algo design & hw/sw modeling process IP Tuning & U.C. Test

  • Block Level

uP RTL Core

eAlgo SW

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SLIDE 13

An Integrated HL Design Methodology: Key to High Design Productivity

  • Subsystem Level

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C2RTL Synthesis

IP SS Virtual Platform SW Dev Ref C Design System Validation

Traffic Performance Analysis SoC Virtual Platform System SW Dev

timing power

Other TLM IP models Transactor Syn C Design C Cov Model RTL Design

RTL Cov Model

TLM Wrapper

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SLIDE 14

Design Examples

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Design Ref C LoC Synth C LoC Area Hand RTL LoC Area Speed (MHz) Power

Block1 1263 1794 51.72 5152 51.26 266 Block2 1954 3722 296,436 10988 371,855 400/200 Block3 4281 12578 686,567 38110 400 Block4 3155 9498 774,726 28780 400 Block1: apple to apple comparison using the same micro-architecture Block2: HLS design uses micro-architecture optimization to increase the clock speed and decrease the area while keeping the same throughput Block3,4: LoC for Hand RTL is extrapolated (3x). It is beyond a single designer’s reach within a reasonable time period

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SLIDE 15

Remarks

  • Moving to High Level (C) design provides significant

efficiency and effectiveness.

  • High Level Synthesis tool is an enabling technology, upon

which an integrated high level design flow can be built.

  • An integrated high level design flow includes h/w and s/w

co-modeling, synthesis and verification techniques, that allow the majority of design work being done in the high level C domain.

  • An integrated high level design flow should seamlessly

work or interface with the existing RTL design methodology and flow.

  • Thus, it includes the existing RTL flow such that it

simplifies the execution of the existing RTL flow.

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