Algorithmic Complexity of Correctness Testing in MC-Scheduling
Rany Kahil, Dario Socci, Peter Poplavko, Saddek Bensalem
VERIMAG, University of Grenoble Alpes
RTNS’18
Kahil et al. (VERIMAG) Correctness Testing in MCS RTNS’18 1 / 27
Algorithmic Complexity of Correctness Testing in MC-Scheduling Rany - - PowerPoint PPT Presentation
Algorithmic Complexity of Correctness Testing in MC-Scheduling Rany Kahil, Dario Socci, Peter Poplavko, Saddek Bensalem VERIMAG, University of Grenoble Alpes RTNS18 Kahil et al. (VERIMAG) Correctness Testing in MCS 1 / 27 RTNS18 Our
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◮ J1 executes ◮ J2 executes Kahil et al. (VERIMAG) Correctness Testing in MCS RTNS’18 13 / 27
2 4 6 8 10 12 14 J1 (5 units)
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◮ J2 does not signal termination before it executes for 5 time units ◮ J3 does not signal termination before it executes for 2 time units
2 4 6 8 10 12 14 J1 (5 units) J2 + J3 (7 units) Deadline Miss
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2 4 6 8 10 12 14 J2 (5 units)
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◮ J1 does not signal termination before it executes for 7 time units ◮ J3 does not signal termination before it executes for 3 time units
2 4 6 8 10 12 14 J2 (5 units) J1 + J3 (10 units) Deadline Miss
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◮ In a dual-critical system it has two tables the LO and HI* ◮ The schedule starts by using the LO table and in case of a mode
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LO HI* 2 4 6 8 10 12 14 Criticality Mode Time J1 J2 J3 J2 J1 J1 J3 J3 J1 J1
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◮ Total cost = num scenarios x num events per scenario
◮ The cost of CCT is at least cubic in general ◮ For FPM the cost is at least quadratic
◮ The cost of ECT is at least quadratic in general ◮ For FPM the cost is n log n Kahil et al. (VERIMAG) Correctness Testing in MCS RTNS’18 17 / 27
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◮ Two policies are equivalent if they successfully schedule the same
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1 T LO
2 T HI∗
3 T HI∗
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◮ Event.LO-START and Event.LO-STOP mark the beginning and
◮ Event.Disable used to remove a job from the ready queue
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HI* LO 1 2 3 4 5 6 7 8 Mode Time ECT Test for Mode-Aware EDF Policy J1 J4 J2 J3 J1 Kahil et al. (VERIMAG) Correctness Testing in MCS RTNS’18 25 / 27
HI* LO 1 2 3 4 5 6 7 8 Mode Time ECT Test for Mode-Aware EDF Policy J1 J4 J2 J3 J1 J4 Deadline Miss Kahil et al. (VERIMAG) Correctness Testing in MCS RTNS’18 25 / 27
c3 c2 c1 1 2 3 4 5 6 7 8 Scenario Time Mode-Aware EDF Policy J1 J4 Deadline Miss J1 J4 J2 J3 J1 J4 J2 J3 Kahil et al. (VERIMAG) Correctness Testing in MCS RTNS’18 25 / 27
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