A Write-friendly Hashing Scheme for Non-volatile Memory Systems - - PowerPoint PPT Presentation

Pengfei Zuo and Yu Hua

A Write-friendly Hashing Scheme for Non-volatile Memory Systems

Huazhong University of Science and Technology, China

Non-volatile Memory

SRAM DRAM PCM RRAM STT-RAM Non-volatile N N Y Y Y Read (ns) 1 10 20~70 10 2~20 Write (ns) 1 10 150~220 50 5~35 Standby Power High High Low Low Low Scalability (nm) 20 20 5 11 32 Endurance (10^N) > 15 > 15 7~8 8~10 12~15

• NVMs are expected to replace DRAM and SRAM
• NVMs vs. DRAM & SRAM

 No-volatile, high scalability, and low standby power X Limited endurance and asymmetric properties

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Rethinking Data Structures on NVMs

• How could in-memory and in-cache data structures

be modified to efficiently adapt to NVMs?

• Previous work mainly focuses on tree-based structures

 CDDS-tree (FAST 2011)  NV-tree (FAST 2015)  wB+-tree (VLDB 2015)  FP-tree (SIGMOD 2016)  Write Optical Radix Tree (FAST 2017)

• Hash tables are also widely used in main memory

and caches

 Main memory database  In-memory key-value store, e.g., Memcached, Redis  In-cache index (ICS 2014, MICRO 2015)

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Existing Hashing Schemes on NVMs

a b c d e g f h

7 1 2 3 4 5 6

f a d e b c

7 1 2 3 4 5 6 7 1 2 3 4 5 6

a b

7 1 2 3 4 5 6

x

h1(x) h2(x)

Evict

(a) Chained Hashing (b) Linear Probing (c) 2-choice Hashing (d) Cuckoo Hashing

x

h1(x) h2(x)

Insertion Deletion  Extra Writes Deletion  Extra Writes Insertion  Extra Writes Low Space Utilization: ~35%

• Our Design Goals

 Minimize NVM writes while ensuring high performance 4/20

Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method without extra NVM writes Deliver high performance on space utilization and request latency

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Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method resulting in no extra NVM writes Deliver high performance on space utilization and request latency

Level 4 Level 3 Level 2 Level 1 Level 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Addressable cells by hash functions Un-addressable, shared standby cells

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Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method resulting in no extra NVM writes Deliver high performance on space utilization and request latency

Level 4 Level 3 Level 2 Level 1 Level 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Problem: One path can only deal with at most L hash collisions

Insertion and deletion without extra modifications and data movements

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Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method resulting in no extra NVM writes Deliver high performance on space utilization and request latency

Level 4 Level 3 Level 2 Level 1 Level 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X

h1(x) h2(x)

Using two different hash functions to compute two paths  high space utilization

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Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method resulting in no extra NVM writes Deliver high performance on space utilization and request latency

Level 4 Level 3 Level 2 Level 1 Level 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X

h1(x) h2(x)

Problem: Each query may probe many nodes in a high tree

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Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method resulting in no extra NVM writes Deliver high performance on space utilization and request latency

Level 4 Level 3 Level 2 Level 1 Level 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Observation: The bottom levels provide a few standby positions while increasing the length of the read path. Path Shortening: Removing multiple levels in the bottom.

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Our Scheme: Path Hashing

 Position Sharing  Double-path Hashing  Path Shortening

A novel hash-collision resolution method resulting in no extra NVM writes Deliver high performance on space utilization and request latency

Level 4 Level 3 Level 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Observation: The bottom levels provide a few standby positions while increasing the length of the read path. Path Shortening: Removing multiple levels in the bottom.

Evaluation: Reserving a small part of levels can also achieve a high space tilization.

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Physical Storage Structure of Path Hashing

Level 4 Level 3 Level 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Level 4 Level 3 Level 2

An array: 12/20

Physical Storage Structure of Path Hashing

Level 4 Level 3 Level 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Level 4 Level 3 Level 2

An array:

A[4] A[16+4/2] A[16+8+4/2/2]

• No pointers
• The nodes in a path can be accessed in parallel for

insertion, query and deletion

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Experimental Configurations

• Gem5: a full system simulator
• NVMain: a main memory simulator for NVMs
• Datasets: Random Number, Document Word, Fingerprint

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NVM Writes

7.3 1 2 3 4 0.6 0.8

• No. of Written Lines

Load Factor Chained Linear 2-choice Cuckoo Path 14.2 2 4 6 8 10 0.6 0.8

• No. of Written Lines

Load Factor Chained Linear 2-choice Cuckoo Path

RandomNum DocWord

No extra writes No extra writes

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Space Utilization

0% 20% 40% 60% 80% 100% RandomNum DocWord Fingerprint Space Utilization Ratio Chained 2-choice Cuckoo Path

• Path hashing achieves up to 95% space utilization ratio

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Reserved Levels vs. Space Utilization

30% 40% 50% 60% 70% 80% 90% 100% 3 5 7 9 11 13 15 17 19 21 23 25 Space Utilization Ratio The Number of Reserved Levels RandomNum (L = 22) DocWord (L = 23) Fingerprint (L = 24)

• Reserving a small part of levels can also achieve a high

space utilization ratio

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Request Latency

3.5 0.5 1 1.5 2 2.5 0.6 0.8 Deletion Latency (us) Load Factor Chained Linear P-2-choice P-Cuckoo Path 15.3 1 2 3 4 5 6 0.6 0.8 Insertion Latency (us) Load Factor Chained Linear 2-choice Cuckoo Path

0.2 0.4 0.6 0.8 1 0.6 0.8 Query Latency (us) Load Factor Chained Linear P-2-choice P-Cuckoo Path P-Path 18/20

Conclusion

• Existing main hashing schemes usually cause many

extra writes to NVMs

• We propose a write-friendly hashing scheme, path

hashing, without extra writes while having high performance  Position sharing  Double-path hashing  Path shortening

• Experimental results on gem5 with NVMain

 No extra writes  Up to 95% space utilization ratio  Low request latency

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Thanks! Q&A

Open-source Code: https://github.com/Pfzuo/Path-Hashing E-mail: pfzuo@hust.edu.cn Homepage: http://pfzuo.github.io/about/

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