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[537] Virtual Memory Tyler Harter 9/15/14 Overview Review - PowerPoint PPT Presentation

Mar 25, 2023 •48 likes •1.29k views

[537] Virtual Memory Tyler Harter 9/15/14 Overview Review Scheduling Address Spaces (Chapter 13) Address Translation (Chapter 15) Segmentation (Chapter 16) Review: Schedulers Scheduling Basics Workloads : Schedulers : Metrics :

  1. (free) 0x1010: movl 0x8(%rbp), %edi 4 KB 0x1013: addl $0x3, %edi Program Code 0x1019: movl %edi, 0x8(%rbp) Heap process 1 (free) stack why didn’t we have to 8 KB rewrite the stack addr? (free) 0x3010: movl 0x8(%rbp), %edi 12 KB 0x3013: addl $0x3, %edi Program Code 0x3019: movl %edi, 0x8(%rbp) Heap process 2 (free) stack 16 KB (free)

  2. Problem: How to Run Multiple Processes? Approaches (covered today): 
 Time Sharing 
 Static Relocation 
 Base 
 Base+Bounds 
 Segmentation

  3. Base Idea: translate virtual addresses to physical by adding a fixed offset each time. Store offset in a base register. Each process has a different value in the base register when running. This is a “dynamic relocation” technique

  4. 0 KB 1 KB P1 2 KB same code 3 KB 4 KB P2 5 KB 6 KB

  5. 0 KB base register 1 KB P1 2 KB P1 is running 3 KB 4 KB P2 5 KB 6 KB

  6. 0 KB 1 KB P1 2 KB P2 is running 3 KB base register 4 KB P2 5 KB 6 KB

  7. Virtual Physical 0 KB P1: load 100, R1 1 KB P1 2 KB 3 KB 4 KB P2 5 KB 6 KB

  8. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1 2 KB 3 KB 4 KB P2 5 KB 6 KB

  9. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 P1 2 KB 3 KB 4 KB P2 5 KB 6 KB

  10. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 2 KB 3 KB 4 KB P2 5 KB 6 KB

  11. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 2 KB 3 KB 4 KB P2 5 KB 6 KB

  12. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB 3 KB 4 KB P2 5 KB 6 KB

  13. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 3 KB 4 KB P2 5 KB 6 KB

  14. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 load 2024, R1 3 KB 4 KB P2 5 KB 6 KB

  15. Who Controls the Base Register? Who should do translation with base register? 
 (1) process, (2) OS, or (3) HW Who should modify the base register? 
 (1) process, (2) OS, or (3) HW

  16. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 load 2024, R1 3 KB 4 KB P2 Can P2 hurt P1? 
 5 KB Can P1 hurt P2? 6 KB

  17. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 load 2024, R1 3 KB P1: store 3072, R1 store 4096, R1 4 KB P2 Can P2 hurt P1? 
 5 KB Can P1 hurt P2? 6 KB

  18. Problem: How to Run Multiple Processes? Approaches (covered today): 
 Time Sharing 
 Static Relocation 
 Base 
 Base+Bounds 
 Segmentation

  19. Base+Bounds Idea: contain the address space with a bounds register marking the largest physical address Base register: smallest physical addr Bounds register: largest physical addr OSTEP! What happens if you load/store after bounds?

  20. 0 KB base register 1 KB P1 bounds register 2 KB P1 is running 3 KB 4 KB P2 5 KB 6 KB

  21. 0 KB 1 KB P1 2 KB P2 is running 3 KB base register 4 KB P2 bounds register 5 KB 6 KB

  22. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 load 2024, R1 3 KB P1: store 3072, R1 4 KB P2 5 KB Can P1 hurt P2? 6 KB

  23. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 load 2024, R1 3 KB interrupt OS! P1: store 3072, R1 4 KB P2 5 KB Can P1 hurt P2? 6 KB

  24. Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P2: load 100, R1 load 4196, R1 P1 P2: load 1000, R1 load 5196, R1 2 KB P1: load 100, R1 load 2024, R1 3 KB interrupt OS! P1: store 3072, R1 4 KB P2 5 KB Can P1 hurt P2? 6 KB

  25. 
 
 
 Base+Bounds Pros/Cons Pros? 
 Cons?

  26. 
 Base+Bounds Pros/Cons Pros? 
 - fast + simple 
 - little bookkeeping overhead (2 registers / proc) 
 Cons? 
 - not flexible 
 - wastes memory for large address spaces

  27. 
 Base+Bounds Pros/Cons Pros? 
 - fast + simple 
 - little bookkeeping overhead (2 registers / proc) 
 Cons? 
 - not flexible 
 - wastes memory for large address spaces

  28. 0 KB Program Code 1 KB Heap 2 KB wasted space (free) 15 KB Stack 16 KB

  29. Problem: How to Run Multiple Processes? Approaches (covered today): 
 Time Sharing 
 Static Relocation 
 Base 
 Base+Bounds 
 Segmentation

  30. Segmentation Idea: generalize base+bounds Each base+bound pair is a segment Use different segments for heap and memory 
 - how does this help? 
 - requires more registers! Resize segments as needed 
 - how does this help?

  31. Multi-segment translation One (broken) approach: 
 - have no gaps in virtual addresses 
 - map as many low addresses to the first segment 
 as possible, then as many as possible to the 
 second (on so on)

  32. A tricky example Virtual Physical 0 KB P1: load 100, R1 1 KB P1: heap 2 KB 3 KB 4 KB P1: stack 5 KB 6 KB

  33. A tricky example Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1: heap 2 KB 3 KB 4 KB P1: stack 5 KB 6 KB

  34. A tricky example Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1: load 1024, R1 P1: heap 2 KB 3 KB 4 KB P1: stack 5 KB 6 KB

  35. A tricky example Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1: load 1024, R1 load 4096, R1 P1: heap 2 KB 3 KB 4 KB P1: stack 5 KB 6 KB

  36. A tricky example Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1: load 1024, R1 load 4096, R1 grow 2 KB P1: heap heap 3 KB 4 KB P1: stack 5 KB 6 KB

  37. A tricky example Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1: load 1024, R1 load 4096, R1 2 KB P1: heap P1: load 1024, R1 3 KB 4 KB P1: stack 5 KB 6 KB

  38. A tricky example Virtual Physical 0 KB P1: load 100, R1 load 1124, R1 1 KB P1: load 1024, R1 load 4096, R1 2 KB P1: heap P1: load 1024, R1 load 2048, R1 3 KB 4 KB P1: stack 5 KB 6 KB

  39. Multi-segment translation One (correct) approach: 
 - break virtual addresses into two parts 
 - one part indicates segment 
 - one part indicates offset within segment

  40. Virtual Address For example, say addresses are 14 bits. 
 Use 2 bits for segment, 12 bits for offset An address might look like 201E

  41. Virtual Address For example, say addresses are 14 bits. 
 Use 2 bits for segment, 12 bits for offset An address might look like 2 01E segment 2 offset 30

  42. Virtual Address For example, say addresses are 14 bits. 
 Use 2 bits for segment, 12 bits for offset An address might look like 2 01E Choose some segment numbering, such as 
 0: code+data 
 1: heap 
 2: stack

  43. What is the segment/offset? Segment numbers: 
 0: code+data 
 1: heap 
 2: stack 10 0000 0001 0001 (binary) 
 110A (hex) 
 4096 (decimal)

  44. Virtual Physical 0 KB load 0x2010, R1 1 KB heap (seg1) 2 KB 3 KB 4 KB stack (seg2) 5 KB 6 KB

  45. Virtual Physical 0 KB load 0x2010, R1 4KB + 16 1 KB heap (seg1) 2 KB 3 KB 4 KB stack (seg2) 5 KB 6 KB

  46. Virtual Physical 0 KB load 0x2010, R1 4KB + 16 1 KB load 0x1010, R1 heap (seg1) 2 KB 3 KB 4 KB stack (seg2) 5 KB 6 KB

  47. Virtual Physical 0 KB load 0x2010, R1 4KB + 16 1 KB load 0x1010, R1 1KB + 16 heap (seg1) 2 KB 3 KB 4 KB stack (seg2) 5 KB 6 KB

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