[537] Virtual Memory Tyler Harter 9/15/14 Overview Review - - PowerPoint PPT Presentation

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[537] Virtual Memory Tyler Harter 9/15/14 Overview Review - - PowerPoint PPT Presentation

Mar 25, 2023 48 likes •1.29k views

[537] Virtual Memory Tyler Harter 9/15/14 Overview Review Scheduling Address Spaces (Chapter 13) Address Translation (Chapter 15) Segmentation (Chapter 16) Review: Schedulers Scheduling Basics Workloads : Schedulers : Metrics :

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SLIDE 1

[537] Virtual Memory

Tyler Harter 9/15/14

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SLIDE 2

Overview

Review Scheduling Address Spaces (Chapter 13) Address Translation (Chapter 15) Segmentation (Chapter 16)

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SLIDE 3

Review: Schedulers

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SLIDE 4

Scheduling Basics

Metrics:
 turnaround_time
 response_time
 Schedulers:
 FIFO
 SJF
 STCF
 RR Workloads:
 arrival_time
 run_time

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SLIDE 5

Scheduling Basics

Metrics:
 turnaround_time
 response_time
 Schedulers:
 FIFO
 SJF
 STCF
 RR Workloads:
 arrival_time
 run_time

Project grading will be based on turnaround time!

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SLIDE 6

JOB arrival run A 40 B 20 C 5 10

A B 20 40 60 80 A B C 20 40 60 80 C A B 20 40 60 80 C B

A

20 40 60 80

BCABCABABAAAA

Workload

Schedulers:
 FIFO
 SJF
 STCF
 RR

Timelines

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SLIDE 7

JOB arrival run A 40 B 20 C 5 10

A B 20 40 60 80 A B C 20 40 60 80 C A B 20 40 60 80 C B

A

20 40 60 80

BCABCABABAAAA

Workload

Schedulers:
 FIFO
 SJF
 STCF
 RR

Timelines RR SJF STCF FIFO

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SLIDE 8

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets

Lottery Scheduler

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SLIDE 9

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets winner = random(402)

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SLIDE 10

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets winner = 102

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SLIDE 11

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets is 102 < 1 ? winner = 102

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SLIDE 12

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets is 101 < 1 ? winner = 101

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SLIDE 13

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets is 100 < 100 ? winner = 100

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SLIDE 14

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets is 0 < 200 ? winner = 0

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SLIDE 15

Job A
 (1) Job B
 (1) Job C
 (100) Job D
 (200) Job E
 (100)

402 total tickets is 0 < 200 ?

Run D!

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SLIDE 16

Address Spaces

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SLIDE 17

More Virtualization

Virtual CPU: illusion of private CPU registers


  • 2 lectures

Virtual RAM: illusion of private memory


  • 5 lectures

The 1st “Easy Piece” in OSTEP is virtual CPU+RAM

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SLIDE 18

The Abstraction

A process has a set of addresses that map to bytes This set is called on address space How can we provide a private address space? Extend LDE (limited direct execution) Review: what stuff is in an address space?

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SLIDE 19

Match that Segment!

int x; int main(int argc, char *argv[]) { int y; int *z = malloc(sizeof(int));); }

x main y z code data heap stack

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SLIDE 20

Match that Segment!

int x; int main(int argc, char *argv[]) { int y; int *z = malloc(sizeof(int));); }

x main y z code data heap stack

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SLIDE 21

Match that Segment!

int x; int main(int argc, char *argv[]) { int y; int *z = malloc(sizeof(int));); }

x main y z

  • heap

stack code in OSTEP

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SLIDE 22

(free) Program Code Heap

0 KB 1 KB 2 KB 15 KB

Stack

16 KB

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SLIDE 23

demo0.c output

where is code? 0x100f2ddd0 (4 GB) where is data? 0x100f2e020 (4 GB) where is heap? 0x7ff659403930 (131033 GB) where is stack? 0x7fff5ecd2a1c (131069 GB)

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SLIDE 24

demo1.c disassemble

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SLIDE 25

Memory Accesses

#include <stdio.h> #include <stdlib.h>

  • int main(int argc, char *argv[])

{ int x; x = x + 3; }

_main: 0000000000000000 pushq %rbp 0000000000000001 movq %rsp, %rbp 0000000000000004 movl $0x0, %eax 0000000000000009 movl %edi, 0xfffffc(%rbp) 000000000000000c movq %rsi, 0xfffff0(%rbp) 0000000000000010 movl 0xffffec(%rbp), %edi 0000000000000013 addl $0x3, %edi 0000000000000019 movl %edi, 0xffffec(%rbp) 000000000000001c popq %rbp 000000000000001d ret

  • tool -tv demo1.o

(or objdump on Linux)

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SLIDE 26

Memory Accesses

#include <stdio.h> #include <stdlib.h>

  • int main(int argc, char *argv[])

{ int x; x = x + 3; }

_main: 0000000000000000 pushq %rbp 0000000000000001 movq %rsp, %rbp 0000000000000004 movl $0x0, %eax 0000000000000009 movl %edi, 0xfffffc(%rbp) 000000000000000c movq %rsi, 0xfffff0(%rbp) 0000000000000010 movl 0xffffec(%rbp), %edi 0000000000000013 addl $0x3, %edi 0000000000000019 movl %edi, 0xffffec(%rbp) 000000000000001c popq %rbp 000000000000001d ret

  • tool -tv demo1.o

(or objdump on Linux)

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SLIDE 27

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 %rip = 0x10
 %rbp = 0x200

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SLIDE 28

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 %rip = 0x10
 %rbp = 0x200

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SLIDE 29

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





%rip = 0x10
 %rbp = 0x200

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SLIDE 30

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





%rip = 0x13
 %rbp = 0x200

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SLIDE 31

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





Fetch instruction at addr 0x13
 %rip = 0x13
 %rbp = 0x200

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SLIDE 32

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





Fetch instruction at addr 0x13
 Exec, no load





%rip = 0x13
 %rbp = 0x200

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SLIDE 33

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





Fetch instruction at addr 0x13
 Exec, no load





%rip = 0x19
 %rbp = 0x200

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SLIDE 34

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





Fetch instruction at addr 0x13
 Exec, no load





Fetch instruction at addr 0x19
 %rip = 0x19
 %rbp = 0x200

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SLIDE 35

Memory Accesses

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp)

Memory Accesses:
 Fetch instruction at addr 0x10
 Exec, load from addr 0x208





Fetch instruction at addr 0x13
 Exec, no load





Fetch instruction at addr 0x19
 Exec, store to addr 0x208
 %rip = 0x19
 %rbp = 0x200

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SLIDE 36

Problem: How to Run Multiple Processes?

Addresses are “hardcoded” into process binaries.
 How to avoid collisions? Approaches (covered today):
 Time Sharing
 Static Relocation
 Base
 Base+Bounds
 Segmentation

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SLIDE 37

Time Sharing

We give the illusion of many virtual CPUs by saving
 CPU registers to memory when a process isn’t running We give the illusion of many virtual memories by saving memory to disk when a process isn’t running

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SLIDE 38
  • code

data Program Memory

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SLIDE 39
  • code

data Program Memory code
 data heap

  • stack

Process 1

create

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SLIDE 40
  • code

data Program Memory code
 data heap

  • stack

Process 1

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SLIDE 41
  • code

data Program Memory code
 data heap

  • stack

Process 1

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SLIDE 42
  • code

data Program Memory code
 data heap

  • stack

Process 1

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SLIDE 43
  • code

data Program Memory code
 data heap

  • stack

Process 1 code
 data2 heap2

  • stack2

Process 2

create

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SLIDE 44
  • code

data Program Memory code
 data heap

  • stack

Process 1 code
 data2 heap2

  • stack2

Process 2

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SLIDE 45
  • code

data Program Memory code
 data heap

  • stack

Process 1 code
 data2 heap2

  • stack2

Process 2

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SLIDE 46
  • code

data Program Memory code
 data heap

  • stack

Process 1 code
 data2 heap2

  • stack2

Process 2

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SLIDE 47
  • code

data Program Memory code
 data heap

  • stack

Process 1 code
 data2 heap2

  • stack2

Process 2

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SLIDE 48
  • code

data Program Memory code
 data heap

  • stack

Process 1 code
 data2 heap2

  • stack2

Process 2

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SLIDE 49

Time Sharing

Problems? What schedulers would time sharing work well with? Alternative: space sharing

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SLIDE 50

Problem: How to Run Multiple Processes?

Approaches (covered today):
 Time Sharing
 Static Relocation
 Base
 Base+Bounds
 Segmentation

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SLIDE 51

Static Relocation

Idea: rewrite each program before loading it as a process Each rewrite uses different addresses and pointers Change jumps, loads, etc.
 Can any addresses be unchanged?

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SLIDE 52

Rewrite for Each New Process

0x10: movl 0x8(%rbp), %edi 0x13: addl $0x3, %edi 0x19: movl %edi, 0x8(%rbp) 0x1010: movl 0x8(%rbp), %edi 0x1013: addl $0x3, %edi 0x1019: movl %edi, 0x8(%rbp)

0x3010: movl 0x8(%rbp), %edi 0x3013: addl $0x3, %edi 0x3019: movl %edi, 0x8(%rbp)

rewrite rewrite

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SLIDE 53

(free) Program Code stack Heap (free) Program Code stack Heap (free) (free) (free)

4 KB 8 KB 12 KB 16 KB process 1 process 2 0x1010: movl 0x8(%rbp), %edi 0x1013: addl $0x3, %edi 0x1019: movl %edi, 0x8(%rbp) 0x3010: movl 0x8(%rbp), %edi 0x3013: addl $0x3, %edi 0x3019: movl %edi, 0x8(%rbp)

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SLIDE 54

(free) Program Code stack Heap (free) Program Code stack Heap (free) (free) (free)

4 KB 8 KB 12 KB 16 KB process 1 process 2 0x1010: movl 0x8(%rbp), %edi 0x1013: addl $0x3, %edi 0x1019: movl %edi, 0x8(%rbp) 0x3010: movl 0x8(%rbp), %edi 0x3013: addl $0x3, %edi 0x3019: movl %edi, 0x8(%rbp)

why didn’t we have to rewrite the stack addr?

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SLIDE 55

Problem: How to Run Multiple Processes?

Approaches (covered today):
 Time Sharing
 Static Relocation
 Base
 Base+Bounds
 Segmentation

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SLIDE 56

Base

Idea: translate virtual addresses to physical by adding a fixed offset each time. Store offset in a base register. Each process has a different value in the base register when running. This is a “dynamic relocation” technique

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SLIDE 57

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

same code

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SLIDE 58

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

base register P1 is running

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SLIDE 59

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

base register P2 is running

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SLIDE 60

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 Virtual Physical

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SLIDE 61

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical

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SLIDE 62

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1

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SLIDE 63

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1

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SLIDE 64

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1

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SLIDE 65

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1

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SLIDE 66

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1

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SLIDE 67

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1 load 2024, R1

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SLIDE 68

Who Controls the Base Register?

Who should do translation with base register?
 (1) process, (2) OS, or (3) HW Who should modify the base register?
 (1) process, (2) OS, or (3) HW

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SLIDE 69

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1 load 2024, R1

Can P2 hurt P1?
 Can P1 hurt P2?

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SLIDE 70

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1 load 2024, R1

Can P2 hurt P1?
 Can P1 hurt P2?

P1: store 3072, R1 store 4096, R1

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SLIDE 71

Problem: How to Run Multiple Processes?

Approaches (covered today):
 Time Sharing
 Static Relocation
 Base
 Base+Bounds
 Segmentation

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SLIDE 72

Base+Bounds

Idea: contain the address space with a bounds register marking the largest physical address Base register: smallest physical addr Bounds register: largest physical addr What happens if you load/store after bounds?

OSTEP!

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SLIDE 73

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

base register P1 is running bounds register

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SLIDE 74

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P2 is running base register bounds register

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SLIDE 75

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1 load 2024, R1

Can P1 hurt P2?

P1: store 3072, R1

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SLIDE 76

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1 load 2024, R1

Can P1 hurt P2?

P1: store 3072, R1 interrupt OS!

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SLIDE 77

P1 P2

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P2: load 100, R1 load 4196, R1 P2: load 1000, R1 load 5196, R1 P1: load 100, R1 load 2024, R1

Can P1 hurt P2?

P1: store 3072, R1 interrupt OS!

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SLIDE 78

Base+Bounds Pros/Cons

Pros?
 
 
 
 Cons?

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SLIDE 79

Base+Bounds Pros/Cons

Pros?


  • fast + simple

  • little bookkeeping overhead (2 registers / proc)



 Cons?


  • not flexible

  • wastes memory for large address spaces
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SLIDE 80

Base+Bounds Pros/Cons

Pros?


  • fast + simple

  • little bookkeeping overhead (2 registers / proc)



 Cons?


  • not flexible

  • wastes memory for large address spaces
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SLIDE 81

(free) Program Code Heap

0 KB 1 KB 2 KB 15 KB

Stack

16 KB

wasted space

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SLIDE 82

Problem: How to Run Multiple Processes?

Approaches (covered today):
 Time Sharing
 Static Relocation
 Base
 Base+Bounds
 Segmentation

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SLIDE 83

Segmentation

Idea: generalize base+bounds Each base+bound pair is a segment Use different segments for heap and memory


  • how does this help?

  • requires more registers!

Resize segments as needed


  • how does this help?
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SLIDE 84

Multi-segment translation

One (broken) approach:


  • have no gaps in virtual addresses

  • map as many low addresses to the first segment


as possible, then as many as possible to the
 second (on so on)

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SLIDE 85

P1: heap P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 Virtual Physical

A tricky example

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SLIDE 86

P1: heap P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical

A tricky example

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SLIDE 87

P1: heap P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P1: load 1024, R1

A tricky example

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SLIDE 88

P1: heap P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P1: load 1024, R1 load 4096, R1

A tricky example

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SLIDE 89

P1: heap P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P1: load 1024, R1 load 4096, R1

A tricky example

grow heap

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SLIDE 90

P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P1: load 1024, R1 load 4096, R1 P1: load 1024, R1

A tricky example

P1: heap

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SLIDE 91

P1: stack

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1: load 100, R1 load 1124, R1 Virtual Physical P1: load 1024, R1 load 4096, R1 P1: load 1024, R1 load 2048, R1

A tricky example

P1: heap

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SLIDE 92

Multi-segment translation

One (correct) approach:


  • break virtual addresses into two parts

  • one part indicates segment

  • one part indicates offset within segment
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SLIDE 93

Virtual Address

For example, say addresses are 14 bits.
 Use 2 bits for segment, 12 bits for offset An address might look like 201E

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SLIDE 94

Virtual Address

For example, say addresses are 14 bits.
 Use 2 bits for segment, 12 bits for offset An address might look like 2 01E

segment 2

  • ffset 30
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SLIDE 95

Virtual Address

For example, say addresses are 14 bits.
 Use 2 bits for segment, 12 bits for offset An address might look like 2 01E Choose some segment numbering, such as
 0: code+data
 1: heap
 2: stack

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SLIDE 96

What is the segment/offset?

Segment numbers:
 0: code+data
 1: heap
 2: stack 10 0000 0001 0001 (binary)
 110A (hex)
 4096 (decimal)

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SLIDE 97

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical

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SLIDE 98

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16

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SLIDE 99

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16 load 0x1010, R1

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SLIDE 100

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16 load 0x1010, R1 1KB + 16

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SLIDE 101

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16 load 0x1010, R1 1KB + 16 load 0x1100, R1

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SLIDE 102

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16 load 0x1010, R1 1KB + 16 load 0x1100, R1 1KB + 256

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SLIDE 103

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16 load 0x1010, R1 1KB + 16 load 0x1100, R1 1KB + 256 load 0x1400, R1

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SLIDE 104

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2010, R1 Virtual Physical 4KB + 16 load 0x1010, R1 1KB + 16 load 0x1100, R1 1KB + 256 load 0x1400, R1 interrupt OS!

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SLIDE 105

Stack Growth Problem

Example…

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SLIDE 106

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2000, R1 Virtual Physical

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SLIDE 107

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2000, R1 Virtual Physical 4KB

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SLIDE 108

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2000, R1 Virtual Physical 4KB

grow stack

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SLIDE 109

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2000, R1 Virtual Physical 4KB load 0x2000, R1

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SLIDE 110

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2000, R1 Virtual Physical 4KB load 0x2000, R1 3KB

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SLIDE 111

Stack Growth Problem

Example… Problem: phys = virt_offset + base_reg
 phys is anchored to base_reg, which moves

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SLIDE 112

Stack Growth Problem

Example… Problem: phys = virt_offset + base_reg
 phys is anchored to base_reg, which moves Solution: anchor heap segment to bounds_reg:
 phys = bounds_reg - (max_offset - virt_offset)

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SLIDE 113

Stack Growth Problem

Example… Problem: phys = virt_offset + base_reg
 phys is anchored to base_reg, which moves Solution: anchor heap segment to bounds_reg:
 phys = bounds_reg - (max_offset - virt_offset) Example (with max_offset = FFF)…

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SLIDE 114

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

Virtual Physical

stack’s max_offset = FFF

load 0x2FFE, R1

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SLIDE 115

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

load 0x2FFE, R1 Virtual Physical

stack’s max_offset = FFF

5KB - 1

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SLIDE 116

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

Virtual Physical

stack’s max_offset = FFF

5KB - 1 load 0x2BFF, R1 load 0x2FFE, R1

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SLIDE 117

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

Virtual Physical

stack’s max_offset = FFF

5KB - 1 load 0x2BFF, R1 4KB load 0x2FFE, R1

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SLIDE 118

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

Virtual Physical

stack’s max_offset = FFF

5KB - 1 load 0x2BFF, R1 4KB load 0x2FFE, R1

grow stack

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SLIDE 119

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

Virtual Physical

stack’s max_offset = FFF

5KB - 1 load 0x2BFF, R1 4KB load 0x2FFE, R1 load 0x2BFF, R1

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SLIDE 120

heap (seg1) stack (seg2)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

Virtual Physical

stack’s max_offset = FFF

5KB - 1 load 0x2BFF, R1 4KB load 0x2FFE, R1 load 0x2BFF, R1 4KB

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SLIDE 121

Translation Summary

Heap: phys = base_reg + virt_offset
 Stack: phys = bounds_reg - (max_offset - virt_offset) Anchors:


  • for heap, anchor smallest address to base register

  • for stack, anchor biggest address to bounds register
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SLIDE 122

Code Sharing

Idea: make base/bounds for the code of several processes point to the same physical mem Careful: need extra protection!

code (both)

4 KB 5 KB 6 KB 2 KB 3 KB 1 KB 0 KB

P1 heap P2 heap

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SLIDE 123

Segmentation Pros/Cons

Pros?


  • supports sparse address space

  • code sharing

  • fine grained protection



 Cons?


  • external fragmentation
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SLIDE 124

Conclusion

HW+OS work together to trick processes, giving the illusion of private memory Adding CPU registers for base+bounds extends LDE, so translation is fast (does not always need OS) Next time: solve fragmentation with paging