3-D integration with an intra-cortical electrode array. B.Dierickx 1 - - PowerPoint PPT Presentation

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3-D integration with an intra-cortical electrode array. B.Dierickx 1 - - PowerPoint PPT Presentation

Nov 19, 2022 220 likes •575 views

Presented at PIXEL2018 10-14 December 2018 Academia Sinica Pixel array for Taipei 3-D integration with an intra-cortical electrode array. B.Dierickx 1 , P.Gao 1 , A.Babaiefishani 1 , S.Veijalainen 1 , W.Wang 1 , B.Luyssaert 1 , A.Khan 2 ,

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SLIDE 1

Pixel array for 3-D integration with an intra-cortical electrode array.

B.Dierickx1, P.Gao1, A.Babaiefishani1, S.Veijalainen1, W.Wang1, B.Luyssaert1, A.Khan2, R.Edgington2, K.Sahasrabuddhe2, M.Angle2

1 Caeleste, Mechelen, Belgium 2 Paradromics, San Jose, US

Presented at PIXEL2018 10-14 December 2018 Academia Sinica Taipei

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SLIDE 2

Outline

  • 1. Introduction, purpose

Direct extracellular neuron signal sensing Our approach

  • 2. Pixel design & performance

Sense amplifier design Measured performance

  • 3. Future outlook

In-pixel analog domain filtering Prototype results

2

Brain Data acquisition ROIC 256x256 pixels Micro wire bundle PCB

ADC

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SLIDE 3

Detecting neural events in the brain → by an array of microelectrodes connected to an array of voltage amplifiers → like a large channel count oscilloscope with 10µV 20kHz resolution

  • 1. Introduction: purpose

3

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SLIDE 4

Microwire Electrodes

4

One microwire electrode can record spiking activity from several neurons.

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SLIDE 5

5

Connecting microwires directly to a CMOS array allows for readout, digitization, and multiplexing.

CMOS with Metal Contact Pads

Polished bundle

Recording from microwire electrodes

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SLIDE 6

Press the bundles onto CMOS sensor

6

Exposed wire core 100 mm 100 mm CMOS Sensor w/ metal bond pads Microwire bundle Flexible diaphragm (for alignment)

Bundle before Pressing Bundle after Pressing

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SLIDE 7

7

Parameters Specifications # of neural sensors 65,536 (256x256) Full frame readout up to 39,000 frames/s

  • n 32 analog outputs

Input referred noise < 10 µVrms (100 Hz- 20 kHz) Voltage gain 100 – 800 V/V Input impedance > 1 TΩ Pixel pitch 50 mm

Henry/Argo sensor array

Each pixel contains a high-gain, AC- coupled, low-noise voltage amplifier

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SLIDE 8

14.3mm 15.8mm Pixel array

Column ampl, X-scanner 16 differential output buffers

Y scanner Pixel biasing

Column ampl, X-scanner 16 differential output buffers

50µm

Top electrode to be hybridized to the microwire electrode

Henry

8

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SLIDE 9

→ overall pixel topology → design for compactness & for low noise → sense amplifier → pixel layout → measured performance in the array

  • 2. Pixel design & performance

9

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SLIDE 10

Class-A amplifier with resistive self-biasing

1MegOhm 2…4pF ~1pF

Rfeedback

input

>1MΩ

  • utput

Optimized for 1/f noise: single PMOSFET

10

>1TΩ

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SLIDE 11

Compact high value resistor

11

PRO

  • Compact: a diode-connected MOSFET + a

MOSFET bias current source

  • R=1/gm AC value hardly dependent on

variability of the 1st MOSFET. Dependent on the variability of the bias

  • Can make extremely high R

e.g. 1TΩ for IBIAS=25fA. Needed to make very low RC time: 1TΩ*100fC=0.1s CON

  • Needs an exclusive DC path for the IBIAS
  • Only AC / small signal: << 100mV
  • Not very linear
  • Offset must be solved by AC coupling
  • 1/f noise

𝑆 = 1 𝑕𝑛 = 𝑙𝑈 𝑟. 𝐽𝐶𝐽𝐵𝑇

IBIAS

=

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SLIDE 12

Actual Class-A amplifier

self-biasing with MOSFETs

  • Gain = 10
  • Rload = 1Mohm
  • LNA+LPF input referred noise reaches 10µVRMS

R>1TΩ

  • utput

input

12

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SLIDE 13

Actual Henry pixel topology

13

Electrode LPF to column load/buffer Ib1 Ib2 VDD VCC Rload Self biasing Out In Gm C 3 X

Self biased class-A amplifiers

Columnwire

3 X 1-st order Gm-C LPF

Row select C1

A1

C2 C3

A2

M3 M2 M1

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SLIDE 14

Henry pixel

LNA1 LNA2

14

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SLIDE 15

Total pixel gain and BW

15

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SLIDE 16

16

PSD + input noise histogram

න

100𝐼𝑨 20𝑙𝐼𝑨

Frequency [Hz]

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SLIDE 17

Henry pixel noise

input referred noise of one row of pixels

17

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SLIDE 18

→ recognize pulse shapes by matched filters → design of programmable filters → measured performance of prototypes

  • 3. Future outlook

18

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SLIDE 19

Data reduction == recognize these shapes

19

time

Matched filter

frequency

“matched filters” Approximated by a linear sum of 2nd

  • rder filters

Matched filter Matched filter

time time time gain&phase

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SLIDE 20

Pixel topology

20

Electrode in tissue

Sense amplifier

100x

Lowpass Bandpass Resonant

Q, f, A

Lowpass Bandpass Resonant

Q, f, A

Lowpass Bandpass Resonant

Q, f, A

Lowpass Bandpass Resonant

Q, f, A

Lowpass Bandpass Resonant

Q, f, A

Σ

weights

+ +

  • Σ

weights

+ +

  • Σ

weights

+ +

  • reference

comparator

time stamp

S&H S&H S&H

  • -------------------------- Pixel outputs -------------------

Principal component 1 Principal component 2 Principal component 3

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SLIDE 21

Programmable filters

Filters

  • (resonant) bandpass filter
  • (resonant) lowpass filter
  • summator

Based on “ideal” R+C active filters Actually IBIAS/gm+ C implementations Continuous programmability of center/lowpass frequency, Q and gain, by programming IBIAS

Patent WO 2018/191725 pending

21

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SLIDE 22

The OTA

  • All transistors are minimum

sized, or larger for mismatch

  • Tail current can be adjusted

between <1fA and >1µA

  • Gain = between 100x and 200x

22

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SLIDE 23

Resonant bandpass filter (ideal)

Bandwidth = β Quality factor = ω0/β

23

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SLIDE 24

Actual implementation

Pro: compact layout Pro: easy to implement, pure MOS Pro: input offset free Pro: programmable by current Con: one less degree of freedom (R2 absent): If Q must be large, the difference between the two currents becomes huge. If Q is too small, the center gain H0 becomes small as well.

10µm

24

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SLIDE 25

Sweeping both branch currents (simulation)

  • The two branch currents are

adjusted to obtain the desired Q and resonant frequency

  • C=100fF

25

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SLIDE 26

BPF measurement vs simulation

26

11 13 15 17 19 21 23 25 400 800 1600 Gain [dB] Frequency [Hz] Pex Chip1 Chip2 Chip3 Chip4 7 9 11 13 15 17 19 400 500 600 700 800 900 1000 Peak gain [dB] Frequency [Hz] Monte Carlo vs measurement Monte Carlo Measurement

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SLIDE 27

2nd order low-pass filter

27

5µm

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SLIDE 28

LPF measurement vs simulation

28

  • 10
  • 8
  • 6
  • 4
  • 2

2 4 6 8 200 400 800 1600 Gain [dB] Frequency [Hz] Simulation Chip1 Chip2 Chip3 Chip4 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 600 700 800 900 1000 Peak gain Peak frequency [Hz]

LPF: Monte Carlo vs Measurement

Monte Carlo Measurement

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SLIDE 29

29

  • Pure MOSFET design
  • All transistors have minimum size (except when

needed for matching)

  • Capacitors are 100fF MOS
  • Input stages are PMOSFET source followers
  • By adjusting the currents one can set the SF’s
  • utput impedance, hence the gain of each

branch

  • +

N1 N2 N3 P1 P2 P3

Multi-input differential summator

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SLIDE 30

Summator layout 4 + inputs 4 - inputs

30

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SLIDE 31

Summator: simulation vs. measurement

Three different branches with different gains 0dB, -4.5dB, -9dB Measurement compared with simulation

31

  • 12
  • 10
  • 8
  • 6
  • 4
  • 2

2 4 100 1000 10000

Gain [dB]

Frequency

Meas_0dB Meas_-4.5dB Meas_-9dB Sim_0dB Sim_-4.5dB Sim_-9dB

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SLIDE 32

4 Conclusions

32

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SLIDE 33

Conclusions

  • Unprecedented massive parallel 256x256, 50µm pitch

neural probe ROIC

  • 10µVRMS @ 20kHz bandwidth
  • Compact, in-pixel analog domain filters demonstrated
  • Fully programmable
  • Key design issue: mismatch of MOSFETs causes

variability of frequency, gain and Q

33

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SLIDE 34

Projects sponsored by

Thank you!

34 Grant Number: 1 R43 MH110287-01 Co-PIs: Angle and Melosh DARPA NESD Program Contract Number: N66001-17-4005 PI: Angle