1 Changelog Changes made in this version not seen in fjrst lecture: - PowerPoint PPT Presentation

on design choices textbook choices: memory always goes to ‘M’ port of register fjle RSP +/- 8 uses normal ALU, not seperate adders … you: single cycle/instruction; use supplied register/memory other logic: make it function correctly 28 do you have to do this? no

comparing to yis $ ./hclrs nopjmp_cpu.hcl nopjmp.yo ... ... +--------------------- (end of halted state) ---------------------------+ Cycles run: 7 $ ./tools/yis nopjmp.yo Stopped in 7 steps at PC = 0x1e. Status 'HLT', CC Z=1 S=0 O=0 Changes to registers: Changes to memory: 29

HCLRS summary declare/assign values to wires [ test1: value1; test2: value2; 1: default; ] register banks with register iO : next value on i_name ; current value on O_name fjxed functionality register fjle (15 registers; 2 read + 2 write) memories (data + instruction) Stat register (start/stop/error) 30 MUXes with

mov CPU 0xF opcode immediate immediate + (ALU) +2 +10 write enable MUX from convert opcode fetch decode execute memory writeback PC update convert split PC dstE Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] next R[dstE] Data out dstM next R[dstM] Data Mem. ZF/SF Data in Addr in 31

mov CPU 0xF opcode immediate immediate + (ALU) +2 +10 write enable MUX from convert opcode fetch decode execute memory writeback PC update convert split PC dstE Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] next R[dstE] Data out dstM next R[dstM] Data Mem. ZF/SF Data in Addr in 31

Stages conceptual division of instruction: fetch — read instruction memory, split instruction, compute length decode — read register fjle execute — arithmetic (including of addresses) memory — read or write data memory write back — write to register fjle PC update — compute next value of PC 32

stages and time 1; then 2, 3, and 4 at almost the same time something else f. 1; then 2; then 3 and 4 at almost the same time e. 1; then 3; then 2; then 4 d. 1; then 2; then 3; then 4 c. b. fetch / decode / execute / memory / write back / PC update 1; then 2, 3, and 4 in any order a. Hint: recall how registers, register fjles, memory works 4. PC changes 3. %rsp changes 2. memory changes 1. instruction read Order when these events happen pushq %rax instruction: 33

stages example: nop write back input wire to PC register name of a wire from instruction memory part of output wires stage PC update memory decode fetch nop 34 icode : ifun ← M 1 [ PC ] valP ← PC + 1 ← means putting a value on a wire ← means putting value on PC ← valP

stages example: nop write back input wire to PC register name of a wire from instruction memory part of output wires stage PC update memory decode fetch nop 34 icode : ifun ← M 1 [ PC ] valP ← PC + 1 ← means putting a value on a wire ← means putting value on PC ← valP

stages example: nop write back input wire to PC register name of a wire from instruction memory part of output wires stage PC update memory decode fetch nop 34 icode : ifun ← M 1 [ PC ] valP ← PC + 1 ← means putting a value on a wire ← means putting value on PC ← valP

stages example: nop write back input wire to PC register name of a wire from instruction memory part of output wires stage PC update memory decode fetch nop 34 icode : ifun ← M 1 [ PC ] valP ← PC + 1 ← means putting a value on a wire ← means putting value on PC ← valP

stages example: nop/jmp stage valP valC MUX PC PC update write back memory decode fetch jmp dest nop 35 icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 1 valC ← M 8 [ PC + 1] PC ← valP PC ← valC

stages example: nop/jmp stage valP valC MUX PC PC update write back memory decode fetch jmp dest nop 35 icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 1 valC ← M 8 [ PC + 1] PC ← valP PC ← valC

stages example: nop/jmp stage valP valC MUX PC PC update write back memory decode fetch jmp dest nop 35 icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 1 valC ← M 8 [ PC + 1] PC ← valP PC ← valC

jmp+nop CPU nop nop 1 0 jmp Dest 7 0 Dest 0 dest jmp dest 1 icode valC valP PC not in listing + 1 (nop size) opcode PC dstE Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] next R[dstE] 0 if nop dstM next R[dstM] Data Mem. ZF/SF split MUX 1 if jmp 36

jmp+nop CPU nop nop 1 0 jmp Dest 7 0 Dest 0 dest jmp dest 1 icode valC valP PC not in listing + 1 (nop size) opcode PC dstE Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] next R[dstE] 0 if nop dstM next R[dstM] Data Mem. ZF/SF split MUX 1 if jmp 36

stages example: rmmovq/mrmovq execute setting register fjle input wires to valM assignment means: naming the output of the data memory assignment means: setting address wires to valE and assignment means: but would be harmless naming output wires of register fjle assignment means: PC update stage memory write back 37 decode rmmovq rA, D(rB) mrmovq D(rB), rA fetch icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC setting register number input register fjle and M 8 [ valE ] ← valA valM ← M 8 [ valE ] setting register fjle write reigster number R [ rA ] ← valM PC ← valP PC ← valP setting value input wires to valA and setting memory write enable to 1

stages example: rmmovq/mrmovq execute setting register fjle input wires to valM assignment means: naming the output of the data memory assignment means: setting address wires to valE and assignment means: but would be harmless naming output wires of register fjle assignment means: PC update stage memory write back 37 decode rmmovq rA, D(rB) mrmovq D(rB), rA fetch icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC setting register number input register fjle and M 8 [ valE ] ← valA valM ← M 8 [ valE ] setting register fjle write reigster number R [ rA ] ← valM PC ← valP PC ← valP setting value input wires to valA and setting memory write enable to 1

stages example: rmmovq/mrmovq execute setting register fjle input wires to valM assignment means: naming the output of the data memory assignment means: setting address wires to valE and assignment means: but would be harmless naming output wires of register fjle assignment means: PC update stage memory write back 37 decode rmmovq rA, D(rB) mrmovq D(rB), rA fetch icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC setting register number input register fjle and M 8 [ valE ] ← valA valM ← M 8 [ valE ] setting register fjle write reigster number R [ rA ] ← valM PC ← valP PC ← valP setting value input wires to valA and setting memory write enable to 1

stages example: rmmovq/mrmovq execute setting register fjle input wires to valM assignment means: naming the output of the data memory assignment means: setting address wires to valE and assignment means: but would be harmless naming output wires of register fjle assignment means: PC update stage memory write back 37 decode rmmovq rA, D(rB) mrmovq D(rB), rA fetch icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC setting register number input register fjle and M 8 [ valE ] ← valA valM ← M 8 [ valE ] setting register fjle write reigster number R [ rA ] ← valM PC ← valP PC ← valP setting value input wires to valA and setting memory write enable to 1

stages example: rmmovq/mrmovq execute setting register fjle input wires to valM assignment means: naming the output of the data memory assignment means: setting address wires to valE and assignment means: but would be harmless naming output wires of register fjle assignment means: PC update stage memory write back 37 decode rmmovq rA, D(rB) mrmovq D(rB), rA fetch icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC setting register number input register fjle and M 8 [ valE ] ← valA valM ← M 8 [ valE ] setting register fjle write reigster number R [ rA ] ← valM PC ← valP PC ← valP setting value input wires to valA and setting memory write enable to 1

stages example: rmmovq/mrmovq execute setting register fjle input wires to valM assignment means: naming the output of the data memory assignment means: setting address wires to valE and assignment means: but would be harmless naming output wires of register fjle assignment means: PC update stage memory write back 37 decode rmmovq rA, D(rB) mrmovq D(rB), rA fetch icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC setting register number input register fjle and M 8 [ valE ] ← valA valM ← M 8 [ valE ] setting register fjle write reigster number R [ rA ] ← valM PC ← valP PC ← valP setting value input wires to valA and setting memory write enable to 1

mov CPU 0 rA rB from convert opcode rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 0 F rB mrmovq D(rB), rA 5 rmmovq rA, D(rB) 0xF 4 0 rA rB V D D valP valC valB valA valE valM write enable +10 PC Data Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM] Mem. +2 ZF/SF Data in Addr in Data out split MUX convert opcode immediate immediate + 38

mov CPU 0 rA rB from convert opcode rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 0 F rB mrmovq D(rB), rA 5 rmmovq rA, D(rB) 0xF 4 0 rA rB V D D valP valC valB valA valE valM write enable +10 PC Data Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM] Mem. +2 ZF/SF Data in Addr in Data out split MUX convert opcode immediate immediate + 38

mov CPU 0 rA rB from convert opcode rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 0 F rB mrmovq D(rB), rA 5 rmmovq rA, D(rB) 0xF 4 0 rA rB V D D valP valC valB valA valE valM write enable +10 PC Data Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM] Mem. +2 ZF/SF Data in Addr in Data out split MUX convert opcode immediate immediate + 38

data path versus control path data path — signals carrying “actual data” control path — signals that control MUXes, etc. fuzzy line: e.g. are condition codes part of control path? we will often omit parts of the control path in drawings, etc. 39

SEQ: instruction fetch read instruction memory at PC split into seperate wires: icode:ifun — opcode rA, rB — register numbers valC — call target or mov displacement compute next instruction address: valP — PC + (instr length) 40

instruction fetch add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 41

SEQ: instruction “decode” read registers valA, valB — register values 42

instruction decode (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , addq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 43

instruction decode (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , addq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 43

SEQ: srcA, srcB always read rA, rB? Problems: push rA pop call ret extra signals: srcA, srcB — computed input register MUX controlled by icode 44

SEQ: possible registers to read call , ret icode logic function F (none) %rsp rB srcB MUX %rsp rA pushq , popq %rsp none? rB instruction rA rmmovq , OP q rB none mrmovq none rA cmovCC , rrmovq none none halt , nop , j CC , irmovq srcB srcA 45

SEQ: possible registers to read call , ret icode logic function F (none) %rsp rB srcB MUX %rsp rA pushq , popq %rsp none? rB instruction rA rmmovq , OP q rB none mrmovq none rA cmovCC , rrmovq none none halt , nop , j CC , irmovq srcB srcA 45

instruction decode (2) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 46

SEQ: execute perform ALU operation (add, sub, xor, and) valE — ALU output read prior condition codes Cnd — condition codes based on ifun (instruction type for jCC/cmovCC) write new condition codes 47

using condition codes: cmov ( always ) 1 ( le ) SF | ZF ( l ) SF cc (from instr) rB 0xF dstE NOT 48

execute (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , addq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 49

execute (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , addq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 49

SEQ: ALU operations? no, constants: (rsp +/- 8) computed ALU input values extra signals: aluA, aluB ret call popq pushq rmmovq ALU inputs always valA, valB (register values)? mrmovq valC valB aluB MUX no, inputs from instruction: (Displacement + rB) 50

execute (2) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 51

SEQ: Memory read or write data memory valM — value read from memory (if any) 52

memory (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , rmmovq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 53

memory (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , rmmovq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 53

SEQ: control signals for memory read/write — read enable? write enable? Addr — address mostly ALU output Data — value to write mostly valB 54 tricky cases: popq , ret tricky cases: call , push

memory (2) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 55

SEQ: write back write registers 56

write back (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , pushq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 57

write back (1) (function rA rB ALU aluA aluB valE 8 0 add/sub xor/and of instr.) 0xF write? function of opcode PC+9 instr. length + valP exercise: which of these instructions can this not work for? nop , pushq , mrmovq , popq , call , %rsp 0xF PC next R[dstM] Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data %rsp Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF %rsp 57

SEQ: control signals for WB two write inputs — two needed by popq valM (memory output), valE (ALU output) two register numbers dstM, dstE write disable — use dummy register number 0xF MUX dstE rB F %rsp 58

write back (2a) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 59

write back (2b) add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 60

SEQ: Update PC choose value for PC next cycle (input to PC register) usually valP (following instruction) exceptions: call , j CC , ret 61

PC update add/sub %rsp rA rB ALU aluA aluB valE 8 0 xor/and 0xF (function of instr.) write? function of opcode PC+9 instr. length + valP 0xF %rsp PC dstM Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] next R[dstM] %rsp Data Mem. ZF/SF Stat Data in Addr in Data out valC 0xF 0xF 62

Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for ret ? Exercise: what do they select for call ? Exercise: what do they select for rmmovq ? circuit: setting MUXes length PC+2 9 8 + of opcode instr. PC+9 rA= 8 function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 63

Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for ret ? Exercise: what do they select for call ? Exercise: what do they select for rmmovq ? circuit: setting MUXes length PC+2 9 8 + of opcode instr. PC+9 rA= 8 function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 63

Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for ret ? Exercise: what do they select for call ? Exercise: what do they select for rmmovq ? circuit: setting MUXes length PC+2 9 8 + of opcode instr. PC+9 rA= 8 function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 63

Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for ret ? Exercise: what do they select for call ? circuit: setting MUXes length PC+2 9 8 + of opcode instr. PC+9 rA= 8 function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 64

Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for ret ? Exercise: what do they select for call ? circuit: setting MUXes length PC+2 9 8 + of opcode instr. PC+9 rA= 8 function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for rmmovq ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 64

Exercise: what do they select for rmmovq ? Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for ret ? circuit: setting MUXes PC+2 9 8 + length PC+9 instr. rA= 8 of opcode function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for call ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 65

Exercise: what do they select for rmmovq ? Exercise: what do they select for popq ? Exercise: what do they select for irmovq ? Exercise: what do they select for call ? circuit: setting MUXes PC+2 9 8 + length PC+9 instr. rA= 8 of opcode function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for ret ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 66

Exercise: what do they select for rmmovq ? Exercise: what do they select for popq ? Exercise: what do they select for ret ? Exercise: what do they select for call ? circuit: setting MUXes PC+2 9 8 + length PC+9 instr. rA= 8 of opcode function write? of instr.) M[PC+1] R[9] rB= 9 R[8] xor/and aluA + aluB M[PC+2] add MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select when running addq %r8, %r9 ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … Exercise: what do they select for irmovq ? MUXes — PC, dstM, dstE, aluA, aluB, dmemIn, dmemAddr, … (function add/sub PC dstE ZF/SF Mem. Data next R[dstM] dstM next R[dstE] R[srcB] Addr in R[srcA] srcB srcA register fjle Mem. Instr. Data in Data out 0 rA 8 valE aluB aluA ALU rB %rsp valC 0xF 0xF %rsp %rsp 0xF 0xF 67